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SN74LVT240ANSRE4 Datasheet(PDF) 1 Page - Texas Instruments |
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SN74LVT240ANSRE4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 15 page SN74LVT240A 3.3V ABT OCTAL BUFFER/DRIVER WITH 3STATE OUTPUTS SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) D Supports Unregulated Battery Operation Down To 2.7 V D Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C D Ioff and Power-Up 3-State Support Hot Insertion D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC − DW Tube SN74LVT240ADW LVT240A SOIC − DW Tape and reel SN74LVT240ADWR LVT240A SOP − NS Tape and reel SN74LVT240ANSR LVT240A −40 °C to 85°C SSOP − DB Tape and reel SN74LVT240ADBR LX240A −40 C to 85 C TSSOP − PW Tube SN74LVT240APW LX240A TSSOP − PW Tape and reel SN74LVT240APWR LX240A TVSOP − DGV Tape and reel SN74LVT240ADGVR LX240A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2004, Texas Instruments Incorporated Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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