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PCM1609A Datasheet(PDF) 35 Page - Texas Instruments |
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PCM1609A Datasheet(HTML) 35 Page - Texas Instruments |
35 / 43 page www.ti.com THEORY OF OPERATION B0008-03 + + − Z–1 + + + + + + 8-Level Quantizer − Z–1 IN 8 fS OUT 64 fS + + Z–1 + + Z–1 + PCM1609A SLES145A – AUGUST 2005 – REVISED AUGUST 2006 The DAC section of the PCM1609A is based on a multi-bit delta-sigma architecture. This architecture uses a fourth-order noise shaper and an 8-level amplitude quantizer, followed by an analog low-pass filter. A block diagram of the delta-sigma modulator is shown in Figure 36. This architecture has the advantage of stability and improved jitter tolerance, when compared to traditional 1-bit (2-level) delta-sigma designs. Figure 36. Eight-Level Delta-Sigma Modulator The combined oversampling rate of the digital interpolation filter and the delta-sigma modulator is 32 fS, 64 fS, or 128 fS. The total oversampling rate is determined by the desired sampling frequency. If fS ≤ 96 kHz, then the OVER bit in register 12 can be set to an oversampling rate of 64 fS or 128 fS. If fS > 96 kHz, then the OVER bit can be used to set the oversampling rate to 32 fS or 64 fS. Figure 37 shows the out-of-band quantization-noise plots for both the 64 × and 128× oversampling scenarios. Notice that the 128× oversampling plot shows significantly improved out-of-band noise performance, allowing for a simplified low-pass filter to be used at the output of the DAC. 35 Submit Documentation Feedback |
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