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SN74LV541ATDWR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LV541ATDWR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 18 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) OE1 OE2 To Seven Other Channels A1 Y1 1 19 2 18 SN74LV541AT OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS SCES573A – JUNE 2004 – REVISED AUGUST 2005 This device is ideal for driving bus lines or buffer memory address registers. It features inputs and outputs on opposite sides of the package to facilitate printed circuit board layout. The 3-state control gate is a two-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all corresponding outputs are in the high-impedance state. The outputs provide noninverted data when they are not in the high-impedance state. To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE (EACH BUFFER/DRIVER) INPUTS OUTPUT Y OE1 OE2 A L L L L L L H H H X X Z X H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 2 |
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