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PCI9054-AC50BIF Datasheet(PDF) 3 Page - PLX Technology |
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PCI9054-AC50BIF Datasheet(HTML) 3 Page - PLX Technology |
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3 / 4 page  s Has limited I/O pin leakage at precharge voltage Hot Swap Friendly s Incorporates the Hot Swap Control/Status register (HS_CSR) s Incorporates an Extended Capability Pointer (ECP) mechanism s Incorporates added resources for soft- ware control of ENUM#, the ejector switch, and the status LED, which indi- cates to the user insertion/removal PCI Bus Embedded Host Design Another application for the PCI 9054 is PCI host embedded system designs such as network switches and routers, printer engines, set-top boxes and industrial equipment. In this configuration, the PCI 9054 Data Pipe Architecture allows high performance transfer modes. In addition, the PCI 9054 supports both Type 0 and Type 1 PCI configuration cycles which allows the PCI 9054 to configure other PCI devices or cards in the system. Additional Features General Purpose Bus Master Operation s Advanced Data Pipe Architecture includes DMA engines, PCI Initiator, PCI Target, and PCI messaging functions. s Dual independently programmable Data Pipe Architecture DMA engines with programmable FIFOs. Each channel supports block and scatter/gather DMA modes. s 5V Tolerant Operation-The PCI 9054 requires 3.3 Vcc. It provides 3.3V signal- ing with 5V I/O tolerance on both the PCI and Local Buses. s Programmable Prefetch Counter-The PCI 9054 can be programmed to prefetch data during PCI Initiator and PCI Target operations. The prefetch size can be programmed to match the master burst length or can be used as Read Ahead mode data. The PCI 9054 reads single data (8-, 16-, or 32-bit) if the master initiates a single cycle; otherwise, the PCI 9054 prefetches the programmed size. s Six Programmable FIFOs for concurrent burst transactions s Zero wait state burst operation s Serial EEPROM Interface-Contains an interface for an optional serial EEPROM that can be used to load configuration information. The PCI 9054 can also be configured by a local CPU. s Clock-The Local Bus interface runs from a local TTL clock and asserts the neces- sary internal clocks. This clock runs asynchronously to the PCI clock. s Big/Little Endian Conversion-Supports dynamic switching between Big Endian and Little Endian data for PCI Initiator, PCI Target, DMA, and internal register accesses on the Local Bus s Fully supports the Vital Product Data (VPD) PCI extension-Provides an alternate access method other than Expansion ROM for Vital Product Data s Interrupt Generator- Can assert PCI and local interrupts from external and internal sources s Posted Memory Writes-Supports Posted Memory Writes (PMW) for maximum performance and to avoid potential deadlock situations PCI Bus Operation s PCI Dual-Address Cycle (DAC)-Support (64-bit Address Space) enables 64-bit addressing in 64-bit PCI host systems s PCI Power Management-Supports four power states for PCI functions D0, D1, D2, and D3hot and the Power Management Event interrupt (PME#) s New Capabilities Structure-Supports New Capabilities registers to define additional capabilities of PCI functions Local Bus Operation s Programmable Local Bus-Runs up to 50MHz and supports non-multi- plexed 32-bit address/data, multiplexed 32-bit, and slave accesses of 8-, 16-, or 32-bit Local Bus devices. Allows Local Bus bursting up to 200Mbytes/second. s Three PCI-to-Local Address Spaces-The PCI 9054 supports three PCI-to-Local Address spaces when the PCI 9054 is in PCI Target mode. These spaces (Space 0, Space 1, and Expansion ROM spaces) allow any PCI Bus Master to access the local memory spaces with program- mable wait states, bus width, and burst capabilities. Local Bus I/O Chips (Datacom, Telecom, Storage, etc.) I/O CPU ROM PCI 9054 I/O Accelerator RAM PCI Bus Local Bus PCI Slots PCI I/O I/O Chips (Datacom, Telecom, Storage , etc.) I/O I/O PCI Bus CPU MEM PCI 9054 I/O Accelerator I/O Figure 2. High Performance CompactPCI Adapter Figure 3. PCI Bus Embedded Host Design |
Similar Part No. - PCI9054-AC50BIF |
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Similar Description - PCI9054-AC50BIF |
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