P89CV51RC2FBC datasheet(7/73 Pages) NXP

Part #	P89CV51RC2FBC

Description	8-bit 80C51 5 V low power 64 kB flash microcontroller with 1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals

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Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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7 / 73 page

P89CV51RB2_RC2_RD2_1

Product data sheet

Rev. 01 — 5 October 2007

7 of 73

NXP Semiconductors

P89CV51RB2/RC2/RD2

80C51 with 1 kB RAM, SPI

P2[1]/A9

25

19

I/O

P2[1] — Port 2 bit 1.

O

A9 — Address bit 9.

P2[2]/A10

26

20

I/O

P2[2] — Port 2 bit 2.

O

A10 — Address bit 10.

P2[3]/A11

27

21

I/O

P2[3] — Port 2 bit 3.

O

A11 — Address bit 11.

P2[4]/A12

28

22

I/O

P2[4] — Port 2 bit 4.

O

A12 — Address bit 12.

P2[5]/A13

29

23

I/O

P2[5] — Port 2 bit 5.

O

A13 — Address bit 13.

P2[6]/A14

30

24

I/O

P2[6] — Port 2 bit 6.

O

A14 — Address bit 14.

P2[7]/A15

31

25

I/O

P2[7] — Port 2 bit 7.

O

A15 — Address bit 15.

P3[0] to P3[7]

I/O with

internal

pull-up

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3

pins are pulled HIGH by the internal pull-ups when 1s are written to them

and can be used as inputs in this state. As inputs, Port 3 pins that are

externally pulled LOW will source current (IIL) because of the internal

pull-ups.

P3[0]/RXD

11

5

I/O

P3[0] — Port 3 bit 0.

I

RXD — Serial input port.

P3[1]/TXD

13

7

I/O

P3[1] — Port 3 bit 1.

O

TXD — Serial output port.

P3[2]/INT0

14

8

I/O

P3[2] — Port 3 bit 2.

I

INT0 — External interrupt 0 input.

P3[3]/INT1

15

9

I/O

P3[3] — Port 3 bit 3.

I

INT1 — External interrupt 1 input.

P3[4]/T0

16

10

I/O

P3[4] — Port 3 bit 4.

I

T0 — External count input to timer/counter 0.

P3[5]/T1

17

11

I/O

P3[5] — Port 3 bit 5.

I

T1 — External count input to timer/counter 1.

P3[6]/WR

18

12

I/O

P3[6] — Port 3 bit 6.

O

WR — External data memory write strobe.

P3[7]/RD

19

13

I/O

P3[7] — Port 3 bit 7.

O

RD — External data memory read strobe.

PSEN

32

26

O

Program Store Enable: PSEN is the read strobe for external program

memory. When the device is executing from internal program memory,

PSEN is inactive (HIGH). When the device is executing code from external

program memory, PSEN is activated twice each machine cycle, except that

two PSEN activations are skipped during each access to external data

memory.

Table 3.

P89CV51RB2/RC2/RD2 Pin description …continued

Symbol

Type

Description

PLCC44

TQFP44

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