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74LVC3G04GT Datasheet(PDF) 8 Page - NXP Semiconductors |
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74LVC3G04GT Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 15 page  74LVC3G04_5 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 05 — 5 October 2007 8 of 15 NXP Semiconductors 74LVC3G04 Triple inverter Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 10. Test data Supply voltage Input Load VEXT VCC VI tr =tf CL RL tPLH, tPHL 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 k Ω open 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open |
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