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K7S3218T4C-FECI40 Datasheet(PDF) 7 Page - Samsung semiconductor |
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K7S3218T4C-FECI40 Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 20 page 1Mx36 & 2Mx18 QDRTM II+ b4 SRAM K7S3236T4C K7S3218T4C - 7 - Rev. 1.2 March 2007 Programmable Impedance Output Buffer Operation Output Valid Pin (QVLD) Depth Expansion The Q Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be ready for capturing the data. QVLD is edge aligned with CQ and CQ. Separate input and output ports enables easy depth expansion. Each port can be selected and deselected independently and read and write operation do not affect each other. Before chip deselected, all read and write pending operations are completed. The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to VSS through a precision resistor(RQ). The allowable range of RQ is between 175 Ω and 350Ω The value of RQ (within 15% tolerance) is five times the output impedance desired. For example, 250 Ω resistor will give an output impedance of 50Ω. Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles. In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous behavior in the SRAM. To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles. The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-down. Power-Up/Power-Down Supply Voltage Sequencing Echo clock operation To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ, which are syn- chronized with internal data output. Echo clocks run free during normal operation. The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver. |
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Similar Description - K7S3218T4C-FECI40 |
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