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MAX16048 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX16048 Datasheet(HTML) 6 Page - Maxim Integrated Products |
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6 / 68 page  12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers 6 _______________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (VCC = 3V to 14V, TA = -40°C to +85°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC shorted to GND, SCL/SDA at 0V or 3.3V -1 +1 Input Leakage Current -1 +1 µA Output-Voltage Low VOL ISINK = 3mA 0.4 V Input Capacitance CIN 5pF SMBUS TIMING Serial Clock Frequency fSCL 400 kHz Bus Free Time Between STOP and START Condition tBUF 1.3 µs START Condition Setup Time tSU:STA 0.6 µs START Condition Hold Time tHD:STA 0.6 µs STOP Condition Setup Time tSU:STO 0.6 µs Clock Low Period tLOW 1.3 µs Clock High Period tHIGH 0.6 µs Data Setup Time tSU:DAT 100 ns Output Fall Time tOF 10pF ≤ CBUS ≤ 400pF 250 ns Data Hold Time tHD:DAT From 50% SCL falling to SDA change 0.3 0.9 µs Pulse Width of Spike Suppressed tSP 30 ns JTAG INTERFACE TDI, TMS, TCK Logic-Low Input Voltage VIL Input voltage falling 0.55 V TDI, TMS, TCK Logic-High Input Voltage VIH Input voltage rising 2 V TDO Logic-Output Low Voltage VOL_TDO VDBP ≥ 2.5V, ISINK = 2mA 0.4 V TDO Logic-Output High Voltage VOH_TDO VDBP ≥ 2.5V, ISOURCE = 200mA 2.4 V TDO Leakage Current TDO high impedance -1 +1 µA TDI, TMS Pullup Resistors RJPU Pullup to VDBP 710 13 k Ω Input/Output Capacitance CI/O 5pF JTAG TIMING TCK Clock Period t1 1000 ns TCK High/Low Time t2, t3 50 500 ns TCK to TMS, TDI Setup Time t4 15 ns TCK to TMS, TDI Hold Time t5 15 ns TCK to TDO Delay t6 500 ns TCK to TDO High-Impedance Delay t7 500 ns EEPROM TIMING EEPROM Byte Write Cycle Time tWR (Note 6) 10.5 12 ms Note 1: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at TA = +25°C and TA = +85°C. Specifications at TA = -40°C are guaranteed by design. Note 2: VUVLO is the minimum voltage on VCC to ensure the device is EEPROM configured. Note 3: Applies to RESET, fault, delay, and watchdog timeouts. Note 4: Total unadjusted error is a combination of gain, offset, and quantization error. Note 5: Guaranteed by design. Note 6: An additional cycle is required when writing to configuration memory for the first time. |
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Similar Description - MAX16048 |
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