AD9626BCPZ-250 datasheet(5/36 Pages) AD

Part #	AD9626BCPZ-250

Description	12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter

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AD9626

Rev. 0 | Page 5 of 36

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.25 V, DCS enabled, unless otherwise noted.

Table 3.

AD9626-170

AD9626-210

AD9626-250

Parameter1

Temp

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Unit

CLOCK INPUTS

Logic Compliance

Full

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Full

1.2

V

Differential Input Voltage

Full

0.2

6

0.2

6

0.2

6

V p-p

Input Voltage Range

Full

AVDD −

0.3

AVDD +

1.6

AVDD −

0.3

AVDD +

1.6

AVDD −

0.3

AVDD +

1.6

V

Input Common-Mode Range

Full

1.1

AVDD

1.1

AVDD

1.1

AVDD

V

High Level Input Voltage (VIH)

Full

1.2

3.6

1.2

3.6

1.2

3.6

V

Low Level Input Voltage (VIL)

Full

0

0.8

0

0.8

0

0.8

V

Input Resistance (Differential)

Full

16

20

24

16

20

24

16

20

24

kΩ

Input Capacitance

Full

4

pF

LOGIC INPUTS

Logic 1 Voltage

Full

0.8 ×

AVDD

0.8 ×

AVDD

0.8 ×

AVDD

V

Logic 0 Voltage

Full

0.2 ×

AVDD

0.2 ×

AVDD

0.2 ×

AVDD

V

Logic 1 Input Current (SDIO)

Full

0

μA

Logic 0 Input Current (SDIO)

Full

−60

μA

Logic 1 Input Current

(SCLK, PDWN, CSB, RESET)

Full

55

50

μA

Logic 0 Input Current

(SCLK, PDWN, CSB, RESET)

Full

0

μA

Input Capacitance

25°C

4

pF

LOGIC OUTPUTS2

High Level Output Voltage

Full

DRVDD − 0.05

V

Low Level Output Voltage

Full

GND + 0.05

V

Output Coding

Twos complement, Gray code, or offset binary (default)

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2 LVDS RTERMINATION = 100 Ω.

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