ADSP-21992 datasheet(4/60 Pages) AD

Part #	ADSP-21992

Description	Mixed-Signal DSP Controller with CAN

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Rev. A

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Page 4 of 60

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August 2007

ADSP-21992

an algebraic syntax for ease of coding and readability. A com-

prehensive set of development tools supports program

development.

The block diagram (Figure 2) shows the architecture of the

embedded SHARC core. It contains three independent compu-

tational units: the ALU, the multiplier/accumulator (MAC), and

the shifter. The computational units process 16-bit data from

the register file and have provisions to support multiprecision

computations. The ALU performs a standard set of arithmetic

and logic operations; division primitives are also supported. The

MAC performs single cycle multiply, multiply/add, and multi-

ply/subtract operations. The MAC has two 40-bit accumulators,

which help with overflow. The shifter performs logical and

arithmetic shifts, normalization, denormalization, and derive

exponent operations. The shifter can be used to efficiently

implement numeric format control, including multiword and

block floating-point representations.

Register usage rules influence placement of input and results

within the computational units. For most operations, the data

registers of the computational units act as a data register file,

permitting any input or result register to provide input to any

unit for a computation. For feedback operations, the computa-

tional units let the output (result) of any unit be input to any

unit on the next cycle. For conditional or multifunction instruc-

tions, there are restrictions on which data registers may provide

inputs or receive results from each computational unit. For

more information, see the ADSP-2199x DSP Instruction Set

Reference.

A powerful program sequencer controls the flow of instruction

execution. The sequencer supports conditional jumps, subrou-

tine calls, and low interrupt overhead. With internal loop

counters and loop stacks, the ADSP-21992 executes looped code

with zero overhead; no explicit jump instructions are required

to maintain loops.

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and pro-

gram memory). Each DAG maintains and updates four 16-bit

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is pre- or post-modified by the value of

one of four possible modify registers. A length value and base

address may be associated with each pointer to implement auto-

matic modulo addressing for circular buffers. Page registers in

the DAGs allow circular addressing within 64K word bound-

aries of each of the 256 memory pages, but these buffers may not

cross page boundaries. Secondary registers duplicate all the pri-

mary registers in the DAGs; switching between primary and

secondary registers provides a fast context switch.

Efficient data transfer in the core is achieved with the use of

internal buses:

• Program memory address (PMA) bus

• Program memory data (PMD) bus

• Data memory address (DMA) bus

• Data memory data (DMD) bus

• Direct memory access address bus

• Direct memory access data bus

Figure 2. Block Diagram

DATA

ADDRESS

DATA

ADDRESS

SYSTEM INTERRUPT

CONTROLLER

I/O DATA

I/O REGISTERS

(MEMORY-MAPPED)

CONTROL

STATUS

BUFFERS

I/O PROCESSOR

CACHE

64

24-BIT

JTAG

TEST AND

EMULATION

6

ADDR BUS

MUX

DATA BUS

MUX

16

20

PM ADDRESS BUS

DM ADDRESS BUS

PM DATA BUS

DM DATA BUS

PX

24

16

ADSP-219x DSP CORE

PROGRAM

SEQUENCER

DATA

REGISTER

FILE

MULT

BARREL

SHIFTER

ALU

DMA CONTROLLER

INPUT

REGISTERS

RESULT

REGISTERS

16

16-BIT

INTERNAL MEMORY

24

ADDRESS

DATA

ADDRESS 24 BIT

16 BIT

FOUR INDEPENDENT BLOCKS

PROGRAMMABLE

FLAGS (16)

TIMERS

(3)

3

DMA CONNECT

DMA ADDRESS

EXTERNAL PORT

24 BIT

18

I/O ADDRESS

24

16

24

DMA DATA

EMBEDDED

CONTROL

PERIPHERALS

AND

COMMUNICATIONS

PORTS

DAG1

4

16

DAG2

4

16

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