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ST10F273E Datasheet(PDF) 79 Page - STMicroelectronics

Part # ST10F273E
Description  16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F273E Datasheet(HTML) 79 Page - STMicroelectronics

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ST10F273E
System reset
79/179
20
System reset
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in
Table 49
20.1
Input filter
On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes
shorter than 50ns. On the other side, a valid pulse shall be longer than 500ns to grant that
ST10 recognizes a reset command. In between 50ns and 500ns a pulse can either be
filtered or recognized as valid, depending on the operating conditions and process
variations.
For this reason all minimum durations mentioned in this Chapter for the different kind of
reset events shall be carefully evaluated taking into account of the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input
reset pulse duration, the operating frequency is a key factor. Examples:
For a CPU clock of 64 MHz, 4 TCL is 31.25ns, so it would be filtered. In this case the
minimum becomes the one imposed by the filter (that is 500ns).
For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula
is coherent with the limit imposed by the filter.
Table 49.
Reset event definition
Reset Source
Flag
RPD
Status
Conditions
Power-on reset
PONR
Low
Power-on
Asynchronous hardware reset
LHWR
Low
tRSTIN >
(1)
1.
RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
Synchronous long hardware
reset
High
tRSTIN > (1032 + 12)TCL + max(4 TCL, 500ns)
Synchronous short hardware
reset
SHWR
High
tRSTIN > max(4 TCL, 500ns)
tRSTIN ≤(1032 + 12)TCL + max(4 TCL, 500ns)
Watchdog timer reset
WDTR
(2)
2.
See next
Section 20.1 for more details on minimum reset pulse duration
WDT overflow
Software reset
SWR
(3)
3.
The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD
low inhibits the Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to
Sections
20.4, 20.5 and 20.6).
SRST instruction execution


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