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ST10F273E Datasheet(PDF) 82 Page - STMicroelectronics |
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ST10F273E Datasheet(HTML) 82 Page - STMicroelectronics |
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82 / 179 page  System reset ST10F273E 82/179 Figure 15. Asynchronous power-on RESET (EA = 1) RSTF P0[15:13] P0[12:2] transparent transparent P0[1:0] not t. not transparent FLARST V18 XTAL1 ... ≤2 TCL RST ≤1 ms Latching point of Port0 for system start-up configuration VDD ≥ 1 ms (for on-chip VREG stabilization) RPD IBUS-CS ≤1.2 ms (for resonator oscillation + PLL stabilization) ≤10.2 ms (for crystal oscillation + PLL stabilization) RSTIN (After Filter) ≤500 ns ≥ 50 ns 7 TCL 3..4 TCL (Internal) not t. not t. not t. |
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