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ST10F273E Datasheet(PDF) 85 Page - STMicroelectronics

Part # ST10F273E
Description  16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F273E Datasheet(HTML) 85 Page - STMicroelectronics

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ST10F273E
System reset
85/179
Figure 18.
Asynchronous hardware RESET (EA = 0)
1) Longer than Port0 settling time + PLL synchronization (if needed, that is P0(15:13) changed). Longer than
500ns to take into account of Input Filter on RSTIN pin
2) 3 to 8 TCL depending on clock source selection.
Exit from asynchronous reset state
When the RSTIN pin is pulled high, the device restarts: as already mentioned, if internal
FLASH is used, the restarting occurs after the embedded FLASH initialization routine is
completed. The system configuration is latched from Port0: ALE, RD and WR/WRL pins are
driven to their inactive level. The ST10F273E starts program execution from memory
location 00'0000h in code segment 0. This starting location will typically point to the general
initialization routine. Timing of asynchronous Hardware Reset sequence are summarized in
Figure 17 and Figure 18.
20.3
Synchronous reset (warm reset)
A synchronous reset is triggered when RSTIN pin is pulled low while RPD pin is at high
level. In order to properly activate the internal reset logic of the device, the RSTIN pin must
be held low, at least, during 4 TCL (2 periods of CPU clock): refer also to
Section 20.1 for
details on minimum reset pulse duration. The I/O pins are set to high impedance and
RSTOUT pin is driven low. After RSTIN level is detected, a short duration of a maximum of
12 TCL (six periods of CPU clock) elapses, during which pending internal hold states are
cancelled and the current internal access cycle if any is completed. External bus cycle is
aborted. The internal pull-down of RSTIN pin is activated if bit BDRSTEN of SYSCON
RSTF
P0[15:13]
P0[12:2]
transparent
not t.
transparent
not t.
P0[1:0]
not t.
not transparent
3..8 TCL
RST
Latching point of Port0 for
system start-up configuration
RPD
ALE
not transparent
not transparent
(After Filter)
RSTIN
≤500 ns
≥ 50 ns
≤500 ns
≥ 50 ns
8 TCL
3..4 TCL
1)
2)


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