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ST10F273E Datasheet(PDF) 27 Page - STMicroelectronics |
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ST10F273E Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 179 page  ST10F273E Internal Flash memory 27/179 The table above refers to the configuration when bit ROMS1 of SYSCON register is set. When Bootstrap mode is entered: ● Test-Flash is seen and available for code fetches (address 00’0000h) ● User I-Flash is only available for read and write accesses ● Write accesses must be made with addresses starting in segment 1 from 01'0000h, whatever ROMS1 bit in SYSCON value ● Read accesses are made in segment 0 or in segment 1 depending of ROMS1 value. In Bootstrap mode, by default ROMS1 = 0, so the first 32 KBytes of IFlash are mapped in segment 0. Example: In default configuration, to program address 0, user must put the value 01'0000h in the FARL and FARH registers, but to verify the content of the address 0 a read to 00'0000h must be performed. Next Table 6 shows the Control Register interface composition: This set of registers can be addressed by the CPU. Table 5. Flash modules sectorization(1) 1. Write operations or with ROMS1=’1’ or bootstrap mode Bank Description Addresses Size ST10 bus size B0 Bank 0 Test-Flash (B0TF) 0x0000 0000 - 0x0000 1FFF 8 KB 32-bit (I-BUS) Bank 0 Flash 0 (B0F0) 0x0001 0000 - 0x0001 1FFF 8 KB Bank 0 Flash 1 (B0F1) 0x0001 2000 - 0x0001 3FFF 8 KB Bank 0 Flash 2 (B0F2) 0x0001 4000 - 0x0001 5FFF 8 KB Bank 0 Flash 3 (B0F3) 0x0001 6000 - 0x0001 7FFF 8 KB Bank 0 Flash 4 (B0F4) 0x0001 8000 - 0x0001 FFFF 32 KB Bank 0 Flash 5 (B0F5) 0x0002 0000 - 0x0002 FFFF 64 KB Bank 0 Flash 6 (B0F6) 0x0003 0000 - 0x0003 FFFF 64 KB Bank 0 Flash 7 (B0F7) 0x0004 0000 - 0x0004 FFFF 64 KB Bank 0 Flash 8 (B0F8) 0x0004 0000 - 0x0004 FFFF 64 KB Bank 0 Flash 9 (B0F9) 0x0005 0000 - 0x0005 FFFF 64 KB B1 Bank 1 Flash 0 (B1F0) 0x0006 0000 - 0x0006 FFFF 64 KB Bank 1 Flash 1 (B1F1) 0x0007 0000 - 0x0007 FFFF 64 KB |
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