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ST10F273E Datasheet(PDF) 37 Page - STMicroelectronics |
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ST10F273E Datasheet(HTML) 37 Page - STMicroelectronics |
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37 / 179 page  ST10F273E Internal Flash memory 37/179 5.5.2 Flash non volatile write protection I register low FNVWPIRL (0x0E DFB4) NVR Delivery value: FFFFh 5.5.3 Flash non volatile write protection I register high FNVWPIRH (0x0E DFB6) NVR Delivery value: FFFFh 5.5.4 Flash non volatile access protection register 0 FNVAPR0 (0x0E DFB8) NVR Delivery value: ACFFh 15 14 13 12 11 10 9876543 210 reserved W0P9 W0P8 W0P7 W0P6 W0P5 W0P4 W0P3 W0P2 W0P1 W0P0 RW RW RW RW RW RW RW RW RW RW Table 19. Flash non volatile write protection register low Bit Function W0P(9:0) Write protection bank 0 / sectors 9-0 These bits, if programmed at 0, disable any write access to the sectors of Bank 0 (IFlash). 15 14 13 12 11 10 9876543 210 reserved W1P1 W1P0 RW RW Table 20. Flash non volatile protection register high Bit Function W1P(1:0) Write protection bank 1 / sectors 1-0 These bits, if programmed at 0, disable any write access to the sectors of Bank 1 (IFlash). 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved DBGP ACCP RW RW Table 21. Flash non volatile access protection register 0 Bit Function ACCP Access protection This bit, if programmed at 0, disables any access (read/write) to data mapped inside IFlash Module address space, unless the current instruction is fetched from IFlash. DBGP Debug protection This bit, if erased at 1, allows to by-pass all the protections using the Debug features through the Test Interface. If programmed at 0, on the contrary, all the debug features, the Test Interface and all the Flash Test Modes are disabled. Even STMicroelectronics will not be able to access the device to run any eventual failure analysis. |
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