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TMS320C206 Datasheet(PDF) 10 Page - Texas Instruments

Part # TMS320C206
Description  DIGITAL SIGNAL PROCESSORS
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Manufacturer  TI [Texas Instruments]
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TMS320C206 Datasheet(HTML) 10 Page - Texas Instruments

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TMS320C206, TMS320LC206
DIGITAL SIGNAL PROCESSORS
SPRS065B – JUNE 1998 – REVISED JANUARY 1999
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
Table 3. Legend for the ’C206 Internal Hardware Functional Block Diagram (Continued)
SYMBOL
NAME
DESCRIPTION
ISCALE
Input Data-Scaling
Shifter
16-bit to 32-bit barrel left-shifter. ISCALE (ISFL) shifts incoming 16-bit data 0 to16 positions left, relative to
the 32-bit output within the fetch cycle; therefore, no cycle overhead is required for input scaling operations.
MPY
Multiplier
16
× 16-bit multiplier to a 32-bit product. MPY executes multiplication in a single cycle. MPY operates either
signed or unsigned 2s-complement arithmetic multiply.
MSTACK
Micro Stack
MSTACK provides temporary storage for the address of the next instruction to be fetched when
program-address-generation logic is used to generate sequential addresses in data space.
MUX
Multiplexer
Multiplexes buses to a common input
NPAR
Next Program
Address Register
NPAR holds the program address to be driven out on the PAB on the next cycle.
OSCALE
Output
Data-Scaling
Shifter
32-bit to 16-bit barrel left-shifter. OSCALE (OSFL) shifts the 32-bit accumulator output 0 to 7 bits left for
quantization management and outputs either the 16-bit high- or low-half of the shifted 32-bit data to the
Data-Write Data Bus (DWEB).
PAR
Program Address
Register
PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
operations scheduled for the current bus cycle.
PC
Program Counter
PC increments the value from NPAR to provide sequential addresses for instruction-fetching and sequential
data-transfer operations.
PCTRL
Program
Controller
PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.
PRD
Timer-Period
Register
PRD contains the 16-bit period that is loaded into the timer counter when the counter borrows or when the
reload bit is activated. Reset initializes the PRD to FFFFh.
PREG
Product Register
32-bit register holds results of 16
× 16 multiply.
PSCALE
Product-Scaling
Shifter
0-, 1- or 4-bit left shift or 6-bit right shift of multiplier product. The left-shift options are used to manage the
additional sign bits resulting from the 2s-complement multiply. The right-shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE (PSFL) resides in the path
from the 32-bit product shifter and from either the CALU or the DWEB, and requires no cycle overhead.
SDTR
Synchronous Data
Transmit and
Receive Register
16-bit read/write register used to transmit data from/receive data into the synchronous serial port. This
register functions as the path to the transmit and receive FIFOs of the SSP.
SSP
Synchronous
Serial-Port
SSP is the synchronous serial-port.
SSPCR
Synchronous
Serial-Port Control
Register
SSPCR is the control register for selecting the serial port’s mode of operation.
SSPCT
Synchronous
Serial-Port
Counter Register
SSPCT is the synchronous serial-port counter register.
SSPMC
Synchronous
Serial-Port
Multichannel
Register
SSPMC is the synchronous serial-port multichannel register.
SSPST
Synchronous
Serial-Port
Status Register
SSPST is the synchronous serial-port status register.
STACK
Stack
STACK is a block of memory used for storing return addresses for subroutines and interrupt-service
routines, or for storing data. The ’C20x stack is 16-bit wide and eight-level deep.
TCR
Timer-Control
Register
TCR contains the control bits that define the divide-down ratio, start / stop the timer, and reload the period.
Also contained in TCR is the current count in the prescaler. Reset initializes the timer divide-down ratio
to 0 and starts the timer.


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