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TMP86C847IUG Datasheet(PDF) 5 Page - Toshiba Semiconductor

Part # TMP86C847IUG
Description  8 Bit Microcontroller
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMP86C847IUG Datasheet(HTML) 5 Page - Toshiba Semiconductor

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Table of Contents
TMP86C847IUG
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2. Operational Description
2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Memory Address Map............................................................................................................................... 7
2.1.2 Program Memory (MaskROM).................................................................................................................. 7
2.1.3 Data Memory (RAM)................................................................................................................................. 7
2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.1 Clock Generator........................................................................................................................................ 8
2.2.2 Timing Generator.................................................................................................................................... 10
2.2.2.1 Configuration of timing generator
2.2.2.2 Machine cycle
2.2.3 Operation Mode Control Circuit .............................................................................................................. 11
2.2.3.1 Single-clock mode
2.2.3.2 Dual-clock mode
2.2.3.3 STOP mode
2.2.4 Operating Mode Control ......................................................................................................................... 16
2.2.4.1 STOP mode
2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode
2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
2.2.4.4 SLOW mode
2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.1 External Reset Input ............................................................................................................................... 29
2.3.2 Address trap reset .................................................................................................................................. 30
2.3.3 Watchdog timer reset.............................................................................................................................. 30
2.3.4 System clock reset.................................................................................................................................. 30
3. Interrupt Control Circuit
3.1 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.2 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.1 Interrupt master enable flag (IMF) .......................................................................................................... 34
3.2.2 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 34
3.3 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.1 Interrupt acceptance processing is packaged as follows........................................................................ 37
3.4.2 Saving/restoring general-purpose registers............................................................................................ 38
3.4.2.1 Using PUSH and POP instructions
3.4.2.2 Using data transfer instructions
3.4.3 Interrupt return ........................................................................................................................................ 40
3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.5.1 Address error detection .......................................................................................................................... 41
3.5.2 Debugging .............................................................................................................................................. 41


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