TMS28F200BZT, TMS28F200BZB

262144 BY 8-BIT/131072 BY 16-BIT

BOOT-BLOCK FLASH MEMORIES

SMJS200E – JUNE 1994 – REVISED JANUARY 1998

5

POST OFFICE BOX 1443

main block

Primary memory on the TMS28F200BZx is located in two main blocks. One of the blocks has a storage capacity

for 128K bytes and the other block has a storage capacity for 96K bytes.

command state machine

Commands are issued to the CSM using standard microprocessor write timings. The CSM acts as an interface

between the external microprocessor and the internal WSM. The available commands are listed in Table 1 and

the description of these commands are shown in Table 2. When a program or erase command is issued to the

CSM, the WSM controls the internal sequences and the CSM only responds to status reads. After the WSM

completes its task, the WSM status bit (SB7) is set to a logic-high level (1), allowing the CSM to respond to the

full command set again.

operation

Device operations are selected by entering standard JEDEC 8-bit command codes with conventional

microprocessor timing into an on-chip CSM through I/O pins DQ0 – DQ7. When the device is powered up,

internal reset circuitry initializes the chip to a read-array mode of operation. Changing the mode of operation

requires a command code to be entered into the CSM. Table 1 lists the CSM codes for all modes of operation.

The on-chip status register allows the progress of various operations to be monitored. The status register is

interrogated by entering a read-status-register command into the CSM (cycle 1) and reading the register data

on I/O pins DQ0 – DQ7 (cycle 2). Status-register bits SB0 through SB7 correspond to DQ0 through DQ7.

Table 1. Command State Machine Codes for Device Mode Selection

COMMAND

CODE ON

DQ0 – DQ7†

DEVICE MODE

00h

10h

20h

40h

50h

70h

90h

B0h

D0h

FFh

Invalid / Reserved

Alternate Program Setup

Block-Erase Setup

Program Setup

Clear Status Register

Read Status Register

Algorithm Selection

Erase-Suspend

Erase-Resume/Block-Erase Confirm

Read Array

† DQ0 is the least significant bit. DQ8 – DQ15 can be any valid 2-state

level.