TMS28F200BZT, TMS28F200BZB

262144 BY 8-BIT/131072 BY 16-BIT

BOOT-BLOCK FLASH MEMORIES

SMJS200E – JUNE 1994 – REVISED JANUARY 1998

7

POST OFFICE BOX 1443

status register

(continued)

Table 3. Status-Register Bit Definitions and Functions

STATUS

FUNCTION

DATA

COMMENTS

BIT

FUNCTION

DATA

COMMENTS

SB7

Write state machine status

1 = Ready

If SB7 = 0 (busy), the WSM has not completed an erase or

programming operation. If SB7 = 1 (ready), other polling

operations can be performed. Until this occurs, the other status

bits are not valid If the WSM status bit shows busy (0) the user

SB7

Write-state-machine status

y

0 = Busy

bits are not valid. If the WSM status bit shows busy (0), the user

must periodically toggle E or G to determine when the WSM has

completed an operation (SB7=1) since SB7 is not automatically

updated at the completion of a WSM task.

SB6

Erase-suspend status

(ESS)

1 = Erase suspended

0 = Erase in progress or

completed

When an erase-suspend command is issued, the WSM halts

execution and sets the ESS bit high (SB6 = 1) indicating that the

erase operation has been suspended. The WSM bit is also set

high (SB7 = 1) indicating that the erase-suspend operation has

been successfully completed. The ESS bit remains at a logic-high

level until an erase-resume command is input to the CSM (code

D0h ).

SB5

Erase status

(ES)

1 = Block-erase error

0 = Block-erase good

SB5 = 0 indicates that a successful block-erasure has occurred.

SB5 = 1 indicates that an erase-error has occurred. In this case,

the WSM has completed the maximum allowed erase pulses

determined by the internal algorithm, but this was insufficient to

completely erase the device.

SB4

Program status

(PS)

1 = Byte/word-program error

0 = Byte/word-program good

SB4 = 0 indicates successful programming has occurred at the

addressed block location. SB4 = 1 indicates that the WSM was

unable to correctly program the addressed block location.

SB3

VPP status

(VPPS)

1 = Program abort:

VPP range error

0= VPP good

SB3 provides information on the status of VPP during

programming. If VPP is lower than VPPL after a program or erase

command has been issued, SB3 is set to a 1 to indicate that the

programming operation is aborted. If VPP is between VPPH and

VPPL, SB3 will not be set.

SB2 –

SB0

Reserved

These bits should be masked out when reading the status

register.

byte-wide or word-wide mode selection

The memory array is divided into two parts: an upper-half that outputs data through I/O pins DQ8 – DQ15, and

a lower-half that outputs data through DQ0 – DQ7. Device operation in either byte-wide or word-wide mode is

user-selectable and is determined by the logic state of BYTE. When BYTE is at a logic-high level, the device

is in the word-wide mode and data is written to or read from I/O pins DQ0 – DQ15. When BYTE is at a logic-low

level, the device is in the byte-wide mode and data is written to or read from I/O pins DQ0 – DQ7. In the byte-wide

address pin and selects either the upper- or lower-half of the array. Array data from the upper-half (DQ8 – DQ15 )

and the lower-half (DQ0 – DQ7 ) are multiplexed in order to appear on DQ0 – DQ7. Table 4 and Table 5

summarize operations for word-wide mode and byte-wide mode, respectively.