TMS28F200BZT, TMS28F200BZB

262144 BY 8-BIT/131072 BY 16-BIT

BOOT-BLOCK FLASH MEMORIES

SMJS200E – JUNE 1994 – REVISED JANUARY 1998

9

POST OFFICE BOX 1443

command state machine operations (continued)

During an erase cycle, the CSM responds to status-read and erase-suspend commands. When the WSM has

completed its task, the WSM status bit (SB7) is set to a logic-high level and the CSM responds to the full

command set. The CSM stays in the current command state until the microprocessor issues another command.

clear status register

bit (SB5) of the status register. The clear-status-register command (50h) allows the external microprocessor

to clear these status bits and synchronize them to internal operations. When the status bits are cleared, the

device returns to the read-array mode.

read operations

There are three read operations available: read-array, read-algorithm-selection-code, and read-status-register.

The array is read by entering the command code FFh on DQ0 – DQ7. Control pins E and G must be at a

available on DQ0 – DQ15 (word-wide mode) or DQ0 – DQ7 (byte-wide mode ). Any valid address within any

of the blocks selects that block and allows data to be read from the block.

Algorithm-selection codes are read by entering command code 90h on DQ0 – DQ7. Two bus cycles are

required for this operation: the first to enter the command code and a second to read the device-equivalent

in the “don’t care” category (see Table 2, Table 4, and Table 5).

The status register is read by entering the command code 70h on DQ0 – DQ7. Control pins E and G must be

this operation: one to enter the command code and a second to read the status register. In a given read

cycle, status-register contents are updated on the falling edge of E or G, whichever occurs last within the

cycle.

boot-block programming / erasing

A program-setup command can be aborted by writing FFh (in byte-wide mode) or FFFFh (in word-wide mode)

during the second cycle. After writing FFh or FFFFh during the second cycle, the CSM responds only to

status-reads. When the WSM status bit (SB7) is set to a logic-high level, signifying termination of the

nonprogram operation, all commands to the CSM become valid again.