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STR751FR0H6 Datasheet(PDF) 21 Page - STMicroelectronics |
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STR751FR0H6 Datasheet(HTML) 21 Page - STMicroelectronics |
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21 / 84 page  STR750Fxx STR751Fxx STR752Fxx STR755Fxx Pin description 21/84 91 A4 59 A3 P1.04 / PWM3N / ADC_IN9 I/O TT X XO4 X X Port 1.04 PWM: PWM3 complementary output(4) ADC: analog input 9 92 A3 P1.14 / ADC_IN15 I/O TT X XO8 X X Port 1.14 ADC: analog input 15 93 A2 P1.13 / ADC_IN14 I/O TT X XEIT13 O8 X X Port 1.13 ADC: analog input 14 94 D5 P1.01 / TIM0_TI2 I/O TT X XO2 X X Port 1.01 TIM0: Input Capture / trigger / external clock 2 (remappable to P0.05)(8) 95 E6 P1.00 / TIM0_OC2 I/O TT X XO2 X X Port 1.00 TIM0: Output compare 2 (remappable to P0.04)(8) 96 C4 60 C4 V18 S Stabilization for main voltage regulator. Requires external capacitors 33nF between V18 and VSS18. See Figure 4. To be connected to the 1.8V external power supply when embedded regulators are not used. 97 D4 61 C5 VSS18 S Ground Voltage for the main voltage regulator. 98 D3 62 A2 VSS_IO S Ground Voltage for digital I/Os 99 C3 63 B2 VDD_IO S Supply Voltage for digital I/Os 100 A1 64 A1 P0.03 / TIM2_TI1 / ADC_IN1 I/O TT X XO2 X X Port 0.03 TIM2: Input Capture / trigger / external clock 1 ADC: analog input 1 1. For STR755FVx part numbers, the USB pins must be left unconnected. 2. The non available pins on LQPFP64 and LFBGA64 packages are internally tied to low level. 3. None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O pin and VDD_IO. 4. In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where these functions are listed in the table. 5. It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to NRSTOUT pin (if available) or NRSTIN. 6. After reset, these pins are enabled as JTAG alternate function see (Port reset state on page 16). To use these ports as general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case, debugging these I/Os via JTAG is not possible). 7. There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while for the second one, they are mapped to P0.15/CAN_TX and P0.14/CAN_RX. 8. For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description. Table 6. STR750F pin description (continued) Pin n° Pin name Input Output Main function (after reset) Alternate function OD (3) PP |
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