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TC9WMC1FK Datasheet(PDF) 4 Page - Toshiba Semiconductor |
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TC9WMC1FK Datasheet(HTML) 4 Page - Toshiba Semiconductor |
4 / 16 page TC9WMC1FK/FU,TC9WMC2FK/FU 2007-10-19 4 (3) Write operation (WRITE, ERASE, WRAL, ERAL) The write operation has four modes: Write (WRITE), Erase (ERASE), Write All (WRAL) and Erase All (ERAL). The write operation is triggered when the CS is driven Low after the SK pulse is applied. The SK and DI inputs are disabled during the write operation, so no attempt should be made to transfer instructions at this time. If 16-bit or longer data is transferred to the device, the first 16 bits of data are valid and the remaining bits are ignored. The DO output must be held High or in the high-impedance state when a write instruction is received. A write operation is enabled in program enable mode. (3.1) Verify operation A write operation in all write modes is completed within 10 ms (write cycle tPW), but the typical write cycle is shorter (5 ms). If the completion of the write operation is known, the internal write cycle can be minimized. To accomplish this, a verify operation is performed. (a) Operational description When the CS is brought High following the initiation of a write operation (CS = Low), the write operation status can be seen by monitoring the DO pin. This is called a verify operation and the period during which the CS is held High following the initiation of a write operation is called a verify operation cycle. • DO pin = Low: A write operation is in progress. (busy) • DO pin = High: A write operation has been completed. (ready) After the write operation is completed, and if a start bit is not identified, the DO pin goes to the high-impedance state if the CS is Low. If the CS is Low, the DO pin is driven High. When the write operation is in progress (busy), the SK and DI inputs are disabled. Once the write operation has been completed and a start bit is received, the verify operation is stopped. (b) Two operation methods There are two ways to perform a verify operation. One way is to monitor the DO output successively with the CS driven High until the DO output status changes. The other way is to monitor the DO output and, if no change is evident, the verify operation is stopped (CS = Low). The verify operation is then restarted by the CS being pulled High. In this way, when the DO output is not being monitored, the CPU is free for other operations, thus allowing more efficient design of electronic systems. Figure 2. Read Timing Diagram (TC9WMC2) CS SK 1 2 7 8 9 10 11 12 13 26 27 28 1 1 0 DI DO Hi-Z A5 3 4 5 6 A4 A3 A2 A1 A0 D15 D14 D13 D1 D0 D15 D14 D2 D1 D0 D15 Hi-Z 29 41 42 14 44 43 A6 x |
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