TC9WMC1FK/FU,TC9WMC2FK/FU

2007-10-19

6

(3.3) Erase (ERASE)

The Erase instruction writes all bits in the specified memory location to 1. After the CS is driven

High, a start bit is transferred followed by the ERASE instruction and address. In this mode, data

does not need to be transferred. After the least significant bit (A0) of the address is received on the

falling edge of SK, an erase operation is triggered by the CS being pulled Low.

CS

SK

1 2

7 8 9 10

1

1

1

DI

DO

Hi-Z

A5

3 4 5 6

A4 A3 A2 A1 A0

Hi-Z

Figure 6. Erase Timing Diagram (TC9WMC2)

Busy

Ready

Verify

11

A6

x

CS

SK

1 2

7 8 9

1

1

1

DI

DO

Hi-Z

A5

3 4 5 6

A4 A3 A2 A1 A0

Hi-Z

Figure 5. Erase Timing Diagram (TC9WMC1)

Busy

Ready

Verify