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TC59LM836DKG-33 Datasheet(PDF) 6 Page - Toshiba Semiconductor |
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TC59LM836DKG-33 Datasheet(HTML) 6 Page - Toshiba Semiconductor |
6 / 65 page TC59LM836DKG-30,-33,-40 2005-03-07 6/65 Rev 1.3 NOTES: (1) All voltages referenced to VSS, VSSQ. (2) VREF is expected to track variations in VDDQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC). (3) Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns. (4) Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns. (5) VIH (DC) and VIL (DC) are levels to maintain the current logic state. (6) VIH (AC) and VIL (AC) are levels to change to the new logic state. (7) VID is differential voltage of CLK input level and CLK input level. (8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device. (9) VISO means {VICK (CLK) + VICK ( CLK )} /2 (10) Refer to the figure below. (11) In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC) ± 0.04 V. CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C) SYMBOL PARAMETER MIN MAX Delta UNIT CIN Input pin Capacitance 1.5 3.0 0.25 pF CINC Clock pin (CLK, CLK ) Capacitance 1.5 3.0 0.25 pF CI/O DQ, LDS, UDS, LQS, UQS Capacitance 2.5 3.5 0.5 pF CNC NC pin Capacitance 1.5 pF Note: These parameters are periodically sampled and not 100% tested. VISO (min) VISO (max) VICK VICK Vx Vx Vx Vx Vx VICK VICK CLK CLK VSS |VID (AC)| 0 V Differential VISO VSS VID (AC) |
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