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TC59LM914AMG Datasheet(PDF) 1 Page - Toshiba Semiconductor

Part # TC59LM914AMG
Description  MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TC59LM914AMG Datasheet(HTML) 1 Page - Toshiba Semiconductor

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TC59LM914/06AMG-37,-50
2004-08-20
1/59
Rev 1.0
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
512Mbits Network FCRAM1 (SSTL_18 / HSTL_Interface)
− 4,194,304-WORDS × 8 BANKS × 16-BITS
− 8,388,608-WORDS × 8 BANKS × 8-BITS
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMG is Fast Cycle
Random Access Memory (Network FCRAMTM) containing 536,870,912 memory cells. TC59LM914AMG is organized
as 4,194,304-words
× 8 banks × 16 bits, TC59LM906AMG is organized as 8,388,608-words × 8 banks × 8 bits.
TC59LM914/06AMG feature a fully synchronous operation referenced to clock edge whereby all operations are
synchronized at a clock input which enables high performance and simple user interface coexistence.
TC59LM914/06AMG can operate fast core cycle compared with regular DDR SDRAM.
TC59LM914/06AMG is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
TC59LM914/06
PARAMETER
-37
-50
CL
= 3
5.5 ns
6.0 ns
CL
= 4
4.5 ns
5.5 ns
tCK
Clock Cycle Time (min)
CL
= 5
3.75 ns
5.0 ns
tRC
Random Read/Write Cycle Time (min)
22.5 ns
27.5 ns
tRAC Random Access Time (max)
22.0 ns
24.0 ns
IDD1S Operating Current (single bank) (max)
280 mA
240 mA
lDD2P Power Down Current (max)
90 mA
80 mA
lDD6
Self-Refresh Current (max)
20 mA
20 mA
Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS
, FN and all address input signals are sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 3.75 ns minimum
Clock: 266 MHz maximum
Data:
533 Mbps/pin maximum
• Fast cycle and Short Latency
• Eight independent banks operation
When BA2 input assign to A14 input, TC59LM914/06AMG can function as 4 bank device
(Keep backward compatibility to 256Mb)
• Bidirectional differential data strobe signal : TC59LM906AMG
• Bidirectional data strobe signal per byte
: TC59LM914AMG
• Distributed Auto-Refresh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS
Latency
= 3, 4, 5
Burst Length
= 2, 4
• Organization: TC59LM914AMG : 4,194,304 words × 8 banks × 16 bits
TC59LM906AMG : 8,388,608 words
× 8 banks × 8 bits
• Power Supply Voltage
VDD:
2.5 V
± 0.125V
VDDQ: 1.4 V ∼ 1.9 V
• 1.8 V CMOS I/O comply with SSTL_18 and HSTL
• Package:
60Ball BGA, 1mm
× 1mm Ball pitch (P−BGA64−1317−1.00AZ)
Notice : FCRAM is trademark of Fujitsu Limited, Japan.


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