TC74AC175F datasheet(4/10 Pages) TOSHIBA

Part #	TC74AC175F

Description	CMOS Digital Integrated Circuit Silicon Monolithic Quad D-Type Flip Flop with Clear

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Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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4 / 10 page

TC74AC175P/F/FN/FT

2007-10-01

4

Electrical Characteristics

DC Characteristics

Ta = 25°C

Ta =

−40 to 85°C

Characteristics

Symbol

Test Condition

VCC

(V)

Min

Typ.

Max

Min

Max

Unit

High-level input

voltage

VIH

―

2.0

3.0

5.5

1.50

2.10

3.85

―

1.50

2.10

3.85

―

V

Low-level input

voltage

VIL

―

2.0

3.0

5.5

―

0.50

0.90

1.65

―

0.50

0.90

1.65

V

IOH = −50 μA

2.0

3.0

4.5

1.9

2.9

4.4

2.0

3.0

4.5

―

1.9

2.9

4.4

―

High-level output

voltage

VOH

VIN

= VIH or

VIL

IOH = −4 mA

IOH = −24 mA

IOH = −75 mA (Note)

3.0

4.5

5.5

2.58

3.94

―

2.48

3.80

3.85

―

V

IOL = 50 μA

2.0

3.0

4.5

―

0.0

0.1

―

0.1

Low-level output

voltage

VOL

VIN

= VIH or

VIL

IOL = 12 mA

IOL = 24 mA

IOL = 75 mA

(Note)

3.0

4.5

5.5

―

0.36

―

0.44

1.65

V

Input leakage

current

IIN

VIN = VCC or GND

5.5

―

±0.1

―

±1.0

μA

Quiescent supply

current

ICC

VIN = VCC or GND

5.5

―

8.0

―

80.0

μA

Note:

This spec indicates the capability of driving 50 Ω transmission lines.

One output should be tested at a time for a 10 ms maximum duration.

Timing Requirements (input: tr = tf = 3 ns)

Ta =

25°C

Ta =

−40 to

85°C

Characteristics

Symbol

Test Condition

VCC (V)

Limit

Unit

Minimum pulse width

(CK)

tw (L)

tw (H)

―

3.3 ± 0.3

5.0 ± 0.5

7.0

5.0

7.0

5.0

ns

Minimum pulse width

( CLR )

tw (L)

―

3.3 ± 0.3

5.0 ± 0.5

7.0

5.0

7.0

5.0

ns

Minimum set-up time

ts

―

3.3 ± 0.3

5.0 ± 0.5

12.0

6.5

12.0

6.5

ns

Minimum hold time

th

―

3.3 ± 0.3

5.0 ± 0.5

0.0

ns

Minimum removal time

( CLR )

trem

―

3.3 ± 0.3

5.0 ± 0.5

7.0

5.0

7.0

5.0

ns

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