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TC74HC259AP Datasheet(PDF) 1 Page - Toshiba Semiconductor |
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TC74HC259AP Datasheet(HTML) 1 Page - Toshiba Semiconductor |
1 / 10 page TC74HC259AP/AF/AFN 2007-10-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC259AP,TC74HC259AF,TC74HC259AFN 8-Bit Addressable Latch The TC74HC259A is a high speed CMOS ADDRESSABLE LATCH fabricated with silicon gate C2MOS technology. It achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The respective bits are controlled by address inputs A, B, and C. When CLEAR input is held high and enable input G is held low, the data is written into the bit selected by address inputs, the other bit hold their previous conditions. When both CLEAR and G held high, writing of all bits is inhibited regardless of adress inputs, and their previous condition are held. When CLEAR is held low and G is held high, all bits are resent to low regardless of the other inputs. When both of CLEAR and G held low, all bits which isn’t selected by adress inputs are resent to low. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 15 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2~6 V • Pin and function compatible with 74LS259 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74HC259AP TC74HC259AF TC74HC259AFN Weight DIP16-P-300-2.54A : 1.00 g (typ.) SOP16-P-300-1.27A : 0.18 g (typ.) SOL16-P-150-1.27 : 0.13 g (typ.) |
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