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TC74HCT74AF Datasheet(PDF) 1 Page - Toshiba Semiconductor |
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TC74HCT74AF Datasheet(HTML) 1 Page - Toshiba Semiconductor |
1 / 8 page TC74HCT74AP/AF/AFN 2007-10-01 1 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT74AP,TC74HCT74AF,TC74HCT74AFN Dual D-Type Flip Flop with Preset and Clear The TC74HCT74A is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL , NMOS and CMOS output voltage levels. The signal level applied to the D INPUT is transferred to Q OUTPUT during the positive going transition of the CLOCK pulse. CLEAR and PRESET are independent of the CLOCK and are accomplished by setting the applopriate input to an “L” level. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: fmax = 53 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 μA (max) at Ta = 25°C • Compatible with TTL outputs: VIH = 2 V (min) VIL = 0.8 V (max) • Wide interfacing ability: LSTTL, NMOS, CMOS • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays: tpLH ∼− tpHL • Pin and function compatible with 74LS74 Pin Assignment Note: xxxFN (JEDEC SOP) is not available in Japan. TC74HCT74AP TC74HCT74AF TC74HCT74AFN Weight DIP14-P-300-2.54 : 0.96 g (typ.) SOP14-P-300-1.27A : 0.18 g (typ.) SOL14-P-150-1.27 : 0.12 g (typ.) |
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