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DAC5681Z

RGCPackage, QFN649x9

(TopView)

Modified 11-Apr-07

PinsdifferentfromDAC5682Z

48

GND

CLKINC

D4P

D4N

D3P

D3N

D2P

D2N

DVDD

D1P

D1N

D0P

D0N

VFUSE

SDO

SDIO

SCLK

SDENB

D12N

D12P

D13N

D13P

D14N

D14P

DVDD

D15N

D15P

IOVDD

SYNCN

SYNCP

CLKIN

CLKVDD

DAC5681Z

SLLS865 – AUGUST 2007

DAC5681Z

RGC PACKAGE

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AVDD

51, 54, 55,

I

Analog supply voltage. (3.3V)

59, 62

BIASJ

57

O

Full-scale output current bias

CLKIN

2

I

Positive external clock input. With the clock multiplier PLL enabled, CLKIN provides lower frequency

reference clock. If the PLL is disabled, CLKIN directly provides clock for DAC up to 1GHz.

CLKINC

3

I

Complementary external clock input.

CLKVDD

1

I

Internal clock buffer supply voltage. (1.8 V)

D[15..0]P

7, 11, 13, 15,

I

LVDS positive input data bits 0 through 15. Each positive/negative LVDS pair has an internal 100

Ω

17, 19, 21,

termination resistor. Order of bus can be reversed via rev_bus bit in CONFIG5 register. Data format

23, 27, 29,

relative to DCLKP/N clock is Double Data Rate (DDR) with two data samples input be DLCKP/N clock

31, 33, 35,

cycle. In dual-channel mode, data for the A-channel is input while DCLKP is high.

37, 40, 42

D15P is most significant data bit (MSB) – pin 7

D0P is least significant data bit (LSB) – pin 42

Copyright © 2007, Texas Instruments Incorporated

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