March 2006 REVISION 09

SH 9 of 31

Technical Reference Note

AIF - PFC Power Factor

Correction Series

DC-DC Converter Module Enable Output (LD ENABLE)

After the PFC power up sequence, the power to the load can be enabled. This can be performed manually or the PFC can

automatically enable the load using the LD ENABLE signal.

OUTPUT

VOLTAGE

LD

ENABLE

Output stabilized

LOW

HIGH

Depends on external inrush current limit circuit

Initially the load is disabled and the LD ENABLE (pin 15) is at 0.4V (LOW). When the PFC power up sequence has

completed, the LD ENABLE voltage goes HIGH. And the LD ENABLE will stay high as long as Vin is above 175Vac or

Vout is above 250V, even if PF_ENABLE is in disable mode. (Please see the application example section at P.25 for the

external circuit to interlock the LD-ENABLE from PF_ENABLE)

The LD ENABLE pin is capable of delivering 2.7mA at 1.5V when HIGH. See electrical specifications for exact figures.

Power Fail Warning

If output voltage can not be maintained at the pre-programmed PFW threshold voltage, the PFW (pin 14) will go from

HIGH to LOW.

INPUT

VOLTAGE

OUTPUT

VOLTAGE

PFW

PFWThreshold

The output of the PFW signal can drive an opto-coupler to provide an isolated signal from primary side to the secondary

side. The nominal factory set PFW threshold is set at 340V.