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MAX15013CASA Datasheet(PDF) 10 Page - Maxim Integrated Products |
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MAX15013CASA Datasheet(HTML) 10 Page - Maxim Integrated Products |
10 / 18 page Minimum Input Pulse Width The MAX15012/MAX15013 use a single-shot level-shifter architecture to achieve low propagation delay. Typical level shifter architecture causes a minimum (high or low) pulse width (tDmin) at the output that may be higher than the logic-input pulse width. For the MAX15012/ MAX15013 devices, the DH minimum high pulse-width (tDmin-DH-H) is lower than the DL minimum low pulse width (tDmin-DL-L) to avoid any shoot-through in the absence of external BBM delay during the narrow pulse at low duty cycle. See Figure 2. At high duty cycle (close to 100%), the DH minimum low pulse width (tDmin-DH-L) must be higher than the DL min- imum low pulse width (tDmin-DL-L) to avoid the overlap and shoot-through. See Figure 3. In case of the MAX15012/MAX15013, there is a possibility of about 40ns overlap if an external BBM delay is not provided. It is recommended to add external delay in the INH path so that the minimum low pulse width seen at INH is always longer than tPW-min. See the Electrical Characteristics table for the typical values of tPW-min. 175V/2A, High-Speed, Half-Bridge MOSFET Drivers 10 ______________________________________________________________________________________ Figure 2. Minimum Pulse-Width Behavior for Narrow Duty-Cycle Input (On-Time < tPW-min) PWMIN DH DL tDMIN-DH-H tDMIN-DL-L INH INL DH HS N DL N VIN VOUT VDD MAX15012B/ MAX15012D/ MAX15013B/ MAX15013D PWMIN IN-BUILT DEAD TIME |
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