AP7217

500mA CMOS LDO

AP7217 Rev. 1

6 of 7

OCTOBER 2007

www.diodes.com

Timing Diagram

20mSec-TYP.

V

IN

VD

OUT

EN

VR

OUT

1.8V

t

RP

Application Note

Input Capacitor

A 1

μF ceramic capacitor is recommended to connect between IN

and GND pins to decouple input power supply glitch and noise.

The amount of the capacitance may be increased without limit. A

lower ESR (Equivalent Series Resistance) capacitor allows the

use of less capacitance, while higher ESR type requires more

capacitance. This input capacitor must be located as close as

possible to the device to assure input stability and less noise. For

PCB layout, a wide copper trace is required for both IN and GND.

Output Capacitor

The output capacitor is required to stabilize and help the transient

response of the LDO. The AP7217 is designed to have excellent

transient response for most applications with a small amount of

output capacitance. The AP7217 is stable with any small ceramic

output capacitors of 1.0

μF or higher value, and the temperature

coefficients of X7R or X5R type. Additional capacitance helps to

reduce undershoot and overshoot during transient. For PCB

layout, the output capacitor must be placed as close as possible

to OUT and GND pins, and keep the leads as short as possible.

ENABLE/SHUTDOWN Operation

The AP7217 is turned on by setting the EN pin high, and is turned

off by pulling it low. If this feature is not used, the EN pin should

be tied to IN pin to keep the regulator output on at all time. To

ensure proper operation, the signal source used to drive the EN

pin must be able to swing above and below the specified

turn-on/off

voltage

thresholds

listed

in

the

Electrical

EN=0

0V

Φ

EN=1

3.3V

Φ

Current Limit Protection

When output current at OUT pin is higher than current limit

threshold, the current limit protection will be triggered and clamp

the output current to approximately 600mA to prevent

over-current and to protect the regulator from damage due to

overheating.

Short circuit protection

When VRout pin is shorted to GND or VRout voltage is less than

200mV, short circuit protection will be triggered and clamp the

output current to approximately 50mA.

---Open-Drain Active-Low reset output---

The AP7217 microprocess (uP) supervisory circuitry asserts a

guaranteed logic-low reset during power-up and power-down.

threshold.