Pin Description

PIN

NAME

FUNCTION

1

GNDIN+

Input Ground for Shielding Input Signal IN+. Not connected internally.

2

IN+

Noninverting Input Signal

3

IN-

Inverting Input Signal

4

GNDIN-

Input Ground for Shielding Input Signal IN-. Not connected internally.

5, 7, 9, 10

N.C.

No Connection. Leave unconnected.

6, 8, 11

GND

Ground

12, 15

Output Circuitry Power Supply

13

OUT-

Inverting Output of Amplifier

14

OUT+

Noninverting Output of Amplifier

16

DISABLE

connected to GND, outputs are enabled.

17

Power Supply to Circuitry other than Input and Output Circuits

18

CZ+

Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed

Description section.

19

CZ-

Filter Capacitor for Offset Correction. Connect CZ between pin 18 and pin 19. See the Detailed

Description section.

20

Input Circuitry Power Supply

EP

EXPOSED

PAD

Exposed Pad. Must be soldered to supply ground for proper electrical and thermal operation.

+3.3V, 10.7Gbps Limiting Amplifier

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5

Detailed Description and

Applications Information

Figure 1 is a functional diagram of the MAX3971A limit-

ing amplifier. The signal path consists of an input buffer

followed by a gain stage and output amplifier. A feed-

back loop provides offset correction by driving the

average value of the differential output to zero.

Gain Stage and Offset Correction

The limiting amplifier provides approximately 42dB

gain. The large gain makes the amplifier susceptible to

small DC offsets, which cause deterministic jitter. A

low-frequency loop is integrated into the limiting ampli-

fier to reduce output offset, typically to less than 2mV.

The external capacitor (CZ) is required for stability and

to set the low-frequency cutoff for the offset correction

loop. The time constant of the loop is set by the product

of an equivalent 20k

Ω on-chip resistor and the value of

the off-chip capacitor (CZ). For stable operation, the

minimum value of CZ is 0.01µF. To minimize pattern-

dependent jitter, CZ should be as large as possible.

For 10Gbps ethernet and SONET applications, the typi-

cal value of CZ is 0.1µF. Keep CZ close to the package

to reduce parasitic inductance.

CML Input Circuit

The input buffer is designed to accept CML input sig-

nals such as the output from the MAX3970 transimped-

ance amplifier. An equivalent circuit for the input is

shown in Figure 2. For lowest deterministic jitter in all

operating conditions, AC-coupling capacitors are rec-

ommended on the input.

MAX3971A

CZ-

CZ+

LOWPASS

FILTER

CZ

OFFSET

CORRECTION

AMP

INPUT

AMPLIFIER

GAIN

42dB

OUTPUT

AMPLIFIER

OUT+

OUT-

IN+

GNDIN+

GNDIN-

IN-

DISABLE

100

Ω

Figure 1. Functional Diagram