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ST10F272B Datasheet(PDF) 99 Page - STMicroelectronics

Part # ST10F272B
Description  16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F272B Datasheet(HTML) 99 Page - STMicroelectronics

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ST10F272B/ST10F272E
System reset
99/181
Figure 29.
SW / WDT bidirectional RESET (EA=0) followed by a HW RESET
20.7
Reset circuitry
Internal reset circuitry is described in
Figure 32. The RSTIN pin provides an internal pull-up
resistor of 50k
Ω to 250kΩ (The minimum reset time must be calculated using the lowest
value).
It also provides a programmable (BDRSTEN bit of SYSCON register) pull-down to output
internal reset state signal (synchronous reset, watchdog timer reset or software reset).
This bidirectional reset function is useful in applications where external devices require a
reset signal but cannot be connected to RSTOUT pin.
This is the case of an external memory running codes before EINIT (end of initialization)
instruction is executed. RSTOUT pin is pulled high only when EINIT is executed.
The RPD pin provides an internal weak pull-down resistor which discharges external
capacitor at a typical rate of 200
µA. If bit PWDCFG of SYSCON register is set, an internal
pull-up resistor is activated at the end of the reset sequence. This pull-up will charge any
capacitor connected on RPD pin.
The simplest way to reset the ST10F272 is to insert a capacitor C1 between RSTIN pin and
VSS, and a capacitor between RPD pin and VSS (C0) with a pull-up resistor R0 between
RPD pin and VDD. The input RSTIN provides an internal pull-up device equalling a resistor of
50k
Ω to 250kΩ (the minimum reset time must be determined by the lowest value). Select C1
that produce a sufficient discharge time to permit the internal or external oscillator and / or
internal PLL and the on-chip voltage regulator to stabilize.
P0[15:13]
not transparent
RSTF
P0[12:8]
transparent
not t.
P0[1:0]
not t.
not transparent
RST
1024 TCL
RSTOUT
At this time RSTF is sampled LOW
so HW Reset is entered
(After Filter)
RSTIN
≤500 ns
≥ 50 ns
ALE
8 TCL
≤500 ns
≥ 50 ns
P0[7:2]
not transparent


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