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TC93P24FG Datasheet(PDF) 9 Page - Toshiba Semiconductor |
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TC93P24FG Datasheet(HTML) 9 Page - Toshiba Semiconductor |
9 / 15 page TC93P24FG 2006-08-31 9 Pin No. Symbol Pin Name Function and Operation Remarks 77 78 DO1 DO2/OUT Phase comparator output /output port PLL phase comparator output pins. In tri-state output, when the programmable counter divider output is higher than the reference frequency, the pins output High level; when the output is lower than the reference frequency, the pins output Low level. When the outputs match, the pins go to high impedance. Because DO1 and DO2 are output in parallel, optimal filter constants can be designed for both the AM and FM bands. The DO2 pin can be programmed to high impedance or set as an output port (OUT). Therefore, lockup time can be improved using the DO1 and DO2 pins or the pins can be effectively used as output ports. Lock-up time can also be improved by using DO1 and DO2 together by setting the pins to High-Speed Lock mode when using a 4.5 MHz oscillator. When the phase difference equals or exceeds ±1.11 µs, DO1 and DO2 output the phase difference pulse. When the phase difference is less than ±1.11 µs, the DO2 output goes to high impedance and only DO1 outputs the phase difference pulse. 79 TEST2 Test mode control input 2 Input pin for controlling Test mode. When the pins are at High level, the device is in Test mode; at Low level, in normal operation. Normally, set the pins to Low level or NC (pull-down resistors are incorporated). 80~83 P6-0 P6-3 I/O port 6 84~87 P7-0 P7-3 I/O port 7 4-bit CMOS I/O ports. Input and output can be programmed in 1-bit units. 88~91 P8-0 P8-3 I/O port 8 4-bit CMOS I/O port. Input and output can be programmed in 1-bit units. As the pins can be pulled up or pulled down by software they can be used as key input pins. When set to an I/O port input, that input can be varied to release Clock Stop or Wait modes or to set the MUTE bit of the MUTE pin to 1. VDD VDD RIN1 VDD VDD Input instruction VDD VDD RIN2 |
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