USB Peripheral/Host Controller

with SPI Interface

_______________________________________________________________________________________

9

Note 1b: In peripheral mode, the MAX3421E performs identically to the MAX3420E with the following enhancements:

1) R16 adds the PULSEWID0 and PULSEWID1 bits to control the INT pulse width in edge interrupt mode

(see Figure 12.) These bits default to the MAX3420E setting of 10.6µs.

2) R21 adds four more GPIO bits.

3) R22 and R23 add general-purpose input pins to the interrupt system. R24 controls the edge polarity.

4) R27 controls the peripheral/host mode and the SEPIRQ bit.

5) When [GPXB:GPXA] = [1:0] and the bit SEPIRQ = 1 (R27 bit 4), the GPX output replaces the BUSACT

signal with a second IRQ pin dedicated to the GPIN pin interrupts.

Table 2. MAX3421E Register Map in Host Mode (HOST = 1) (Note 2)

REG

NAME

b7

b6

b5

b4

b3

b2

b1

b0

acc

R0

—0

0

0

0

0

0

0

0

—

R1

RCVFIFO

b7b6b5b4b3b2b1b0

RSC

R2

SNDFIFO

b7b6b5b4b3b2b1b0

RSC

R3

—0

0

0

0

0

0

0

0

—

R4

SUDFIFO

b7b6b5b4b3b2b1b0

RSC

R5

—0

0

0

0

0

0

0

0

—

R6

RCVBC

0BC6BC5BC4BC3BC2BC1BC0

RSC

R7

SNDBC

0BC6BC5BC4BC3BC2BC1BC0

RSC

R8

—

00

0

0

0

0

0

0

—

R9

—

00

0

0

0

0

0

0

—

R10

—

00

0

0

0

0

0

0

—

R11

—

00

0

0

0

0

0

0

—

R12

—

00

0

0

0

0

0

0

—

R13

USBIRQ

0

VBUSIRQ

NOVBUSIRQ

00

0

0

OSCOKIRQ

RC

R14

USBIEN

0VBUSIE

NOVBUSIE

00

0

0

OSCOKIE

RSC

R15

USBCTL

00

CHIPRES

PWRDOWN

00

0

0

RSC

R16

CPUCTL

PULSEWID1PULSEWID0

00

0

0

0

IE

RSC

R17

PINCTL

EP3INAK

EP2INAK

EP0INAK

FDUPSPIINTLEVEL

POSINTGPXBGPXA

RSC

R18

REVISION

00

0

1

0

0

1

0

R

R19

—

00

0

0

0

0

0

0

—

R20

IOPINS1

GPIN3GPIN2GPIN1GPIN0GPOUT3

GPOUT2

GPOUT1

GPOUT0

RSC

R21

IOPINS2

GPIN7GPIN6GPIN5GPIN4GPOUT7

GPOUT6

GPOUT5

GPOUT4

RSC

R22

GPINIRQ

GPINIRQ7

GPINIRQ6

GPINIRQ5

GPINIRQ4

GPINIRQ3

GPINIRQ2

GPINIRQ1

GPINIRQ0

RC

R23

GPINIEN

GPINIEN7GPINIEN6GPINIEN5GPINIEN4GPINIEN3GPINIEN2

GPINIEN1GPINIEN0

RSC

R24

GPINPOL

GPINPOL7

GPINPOL6

GPINPOL5

GPINPOL4

GPINPOL3

GPINPOL2

GPINPOL1

GPINPOL0

RSC

R25

HIRQ

HXFRDNIRQ

FRAMEIRQ

CONNIRQ

SUSDNIRQ

SNDBAVIRQ

RCVDAVIRQ

RSMREQIRQ

BUSEVENTIRQ

RC

R26

HIEN

HXFRDNIE

FRAMEIE

CONNIE

SUSDNIE

SNDBAVIE

RCVDAVIE

RSMREQIE

BUSEVENTIE

RSC

R27

MODE

DPPULLDN

DMPULLDN

DELAYISOSEPIRQ

SOFKAENAB

HUBPRE

SPEED

HOST = 1

RSC

R28

PERADDR

0b6b5b4b3b2b1b0

RSC

R29

HCTL

SNDTOG1

SNDTOG0

RCVTOG1

RCVTOG0

SIGRSM

BUSSAMPLE

FRMRSTBUSRSTLS

R30

HXFR

HS

ISO

OUTNIN

SETUP

EP3EP2EP1EP0LS

R31

HRSL

JSTATUS

KSTATUS

SNDTOGRD RCVTOGRD

HRSLT3

HRSLT2

HRSLT1

HRSLT0

R

Table 1. MAX3421E Register Map in Peripheral Mode (HOST = 0) (Notes 1a, 1b) (Continued)