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TL507C Datasheet(PDF) 1 Page - Texas Instruments |
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TL507C Datasheet(HTML) 1 Page - Texas Instruments |
1 / 8 page TL507C, TL507l ANALOG-TO-DIGITAL CONVERTER SLAS041 – OCTOBER 1979 – REVISED OCTOBER 1988 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Low Cost D 7-Bit Resolution D Montonicity Over Entire A/D Conversion Range D Ratiometric Conversion D Conversion Speed . . . Approximately 1 ms D Single-Supply Operation... Either Unregulated 8-V to 18-V (VCC2 Input) or Regulated 3.5-V to 6-V (VCC1 Input) D I2L Technology D Power Consumption at 5 V...25 mW Typ D Regulated 5.5-V Output (≤1 mA) description The TL507 is a low-cost single-slope analog-to- digital converter designed to convert analog inputvoltages between 0.25 VCC1 and 0.75 VCC1 into a pulse-width-modulated output code. The device contains a 7-bit synchronous counter, a binary weighted resistor ladder network, an operational amplifier, two comparators, a buffer amplifier, an internal regulator, and necessary logic circuitry. Integrated-injection logic (I2L) technology makes it possible to offer this complex circuit at low cost in a small dual-in-line 8-pin package. In continuous operation, conversion speeds of up to 1000 conversions per second are possible. The TL507 requires external signals for CLK, RESET, and ENABLE. Versatility and simplicity of operation, coupled with low cost, makes this converter especially useful for a wide variety of applications. The TL507C is characterized for operation from 0 °C to 70°C, and the TL507I is characterized for operation from –40 °C to 85°C. Copyright © 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ANALOG INPUT CONDITION OUTPUT ENABLE X VI < 200 mV Vramp > VI > 200 mV VI > Vramp L† H H H H L H L FUNCTION TABLE † Low level on enable also inhibits the reset function. H = high level, L = low level, X = irrelevant A high level on RESET clears the counter to zero, which sets the internal ramp to 0.75 VCC. Internal pulldown resistors keep RESET and ENABLE low when not connected. 1 2 3 4 8 7 6 5 ENABLE CLK GND OUTPUT RESET VCC2 VCC1 ANALOG INPUT P PACKAGE (TOP VIEW) |
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