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STR912FAW44X6 Datasheet(PDF) 21 Page - STMicroelectronics |
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STR912FAW44X6 Datasheet(HTML) 21 Page - STMicroelectronics |
21 / 99 page STR91xFAx32 STR91xFAx42 STR91xFAx44 Functional overview 21/99 Figure 2. Clock control 3.10.2 Reference clock (RCLK) The main clock (fMSTR) can be divided to operate at a slower frequency reference clock (RCLK) for the ARM core and all the peripherals. The RCLK provides the divided clock for the ARM core, and feeds the dividers for the AHB, APB, External Memory Interface, and FMI units. 3.10.3 AHB clock (HCLK) The RCLK can be divided by 1, 2 or 4 to generate the AHB clock. The AHB clock is the bus clock for the AHB bus and all bus transfers are synchronized to this clock. The maximum HCLK frequency is 96 MHz. 3.10.4 APB clock (PCLK) The RCLK can be divided by 1, 2, 4 or 8 to generate the APB clock. The APB clock is the bus clock for the APB bus and all bus transfers are synchronized to this clock. Many of the peripherals that are connected to the AHB bus also use the PCLK as the source for external bus data transfers. The maximum PCLK frequency is 48 MHz. 3.10.5 Flash memory interface clock (FMICLK) The FMICLK clock is an internal clock derived from RCLK, defaulting to RCLK frequency at power up. The clock can be optionally divided by 2. The FMICLK determines the bus bandwidth between the ARM core and the Flash memory. Typically, codes in the Flash memory can be fetched one word per FMICLK clock in burst mode. The maximum FMICLK frequency is 96MHz. MII_PHYCLK 25MHz PHYSEL X1_CPU X1_CPU X1_RTC X2_RTC EXTCLK_T0T1 EXTCLK_T2T3 USB_CLK48M 4-25MHz 48MHz Main OSC RTC OSC fOSC PLL 32.768 kHz fRTC Timer 0 & 1 fPLL fMSTR Master CLK 1/2 1/2 RCLK DIV (1,2,4,8,16,1024) BRCLK To UART USBCLK To USB RCLK AHB DIV (1,2,4) APB DIV) (1,2,4,8) 1/2 HCLK PCLK FMICLK CPUCLK Timer 2 & 3 1/2 EMI_BCLK JRTCLK RTCSEL 32.768 kHz External clock External clock |
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