SiI3726 SATA Port Multiplier

Data Sheet

Silicon Image, Inc.

© 2006 Silicon Image, Inc.

SiI-DS-0121-C1

9

High Speed Serial Interface Optimization

In order to accommodate different system environments, the port multiplier allows the designer to configure the

device PHYs to support various cable/PCB lengths on each serial I/O independently.

PHY Configuration Settings

Table 3 shows the configuration settings and description for each high-speed serial port.

Pre-emphasis and equalization are used to compensate the signal degradation due to increased cable lengths.

Without pre-emphasis or equalization, jitter at the receiver end will increase along with the increase of the cable

length, causing signal degradation and Bit Error Rate problems. The effect may depend on the system

environment. Factors such as cable quality, PCB implementation, receiver load, etc. all affect the signal quality.

Please consult with Silicon Image’s technical support department for more information.

Table 3: PHY Configuration Settings

Serial Port

Signal

Settings and Description

Host Port

HIO[2:0]

HIO[2:0] = 0b000 (Default). PC motherboard to device applications up to 1m internal

cable, external desktop up to 2m external cable ((2 Meter eSATA cable) or short

backplane up to 18 inch of FR4 (0.012 mil trace width with 1 oz copper)

HIO[2:0] = 0b001: Tx amplitude will be 100mV lager than 000 setting

HIO[2:0] = 0b010 – 0b100 (Reserved. please consult with Silicon Image technical support

for this detail): external desktop up to 4m external cable or short backplane up to 30 inch

of FR4 (0.012 mil trace width with 1 oz copper)

0b 010: Only pre-emphasis enabled

0b 011: Only equalization enabled

0b111: Both pre-emphasis and equalization enabled

HIO[2:0] = 0b101 – 0b111 (Reserved. Contact Silicon Image Technical Support for

details): external desktop longer than 4m external cable or short backplane longer than 30

inch of FR4 (0.012 mil trace width with 1 oz copper)

0b010: Only pre-emphasis enabled

0b011: Only equalization enabled

0b111: Both pre-emphasis and equalization enabled

Device #0

DAIO[1:0]

Device #1

DBIO[1:0]

Device #2

DCIO[1:0]

Device #3

DDIO[1:0]

Device #4

DEIO[1:0]

DxIO[1:0] = 0b00 (Default): PC motherboard to device applications up to 1m internal

cable, external desktop up to 2m external cable (2 Meter eSATA cable) or short

backplane up to 18 inch of FR4 (0.012 mil trace width with 1 oz copper)

DxIO[1:0] = 0b01: Tx amplitude will be 100mV lager than 00 setting

DxIO[1:0] = 0b10 (Reserved. Contact Silicon Image Technical Support): external desktop

up to 4m external cable or short backplane up to 30 inch of FR4 (0.012 mil trace width

with 1 oz copper). Both pre-emphasis and equalization are enabled

DxIO[1:0] = 0b11 (Reserved. Contact Silicon Image Technical Support): external desktop

longer than 4m external cable or short backplane longer than 30 inch of FR4 (0.012 mil

trace width with 1 oz copper). Both pre-emphasis and equalization are enabled

Tx Eye Measurement

The SiI 3726 SATA Port Multiplier has the capability to output random (scrambled) and deterministic data patterns

(primitives) to downstream devices bypassing the OOB sequence for eye measurement testing.

Upon completing the device enumeration process, the port multiplier outputs COM_RESET/COMINIT periodically.

This implementation maintains compatibility with the SATA compliant host/device and enables hot plug support.

But this implementation also prevents evaluating the Tx eye quality by connecting it directly to the oscilloscope.

By bypassing the OOB sequence after the host completes the device enumeration sequence, the Tx will output a

random data pattern. The port multiplier can bypass the OOB sequence by setting pin Y12 (OOB_BP) to high. In

addition to this, if CONT primitive is disabled by setting pin Y11 (CONT_DIS) to high, the Tx will output a

deterministic data pattern. The output generation (1.5 G or 3.0 G) can be selected by pin W12 (TX_GEN).

The random data pattern is a scrambled data pattern and useful for eye mask testing. The deterministic pattern is

a repetitive pattern of primitives and is useful for jitter analysis. The primitive is normally synchronous and

includes Align primitives every 256DWORDs.