ICM7562/7542/7522

Rev. A6

ICmic reserves the right to change specifications without prior notice

7

DETAILED DESCRIPTION

The ICM7562 is a 12-bit voltage output Dual DAC. The

ICM7542 is the 10-bit version of this family and the

ICM7522 is the 8-bit version. These devices have a 16-bit

data-in shift register and each DAC has a double buffered

input.

This family of DACs has a guaranteed monotonic behavior.

The operating supply range is from 2.7V to 5.5V.

Reference Input

The reference input accepts positive DC and AC signals.

The voltage at REFIN sets the full-scale output voltage of

both the DACs. The reference input voltage range is from 0

to VDD-1.5V. The impedance at this pin is very high

(greater than 10 M Ohm). Each DACs output amplifier is

configured in a gain of 2 configuration. This means that the

the output voltage for any code, use the following equation.

Where D is the numeric value of DAC’s decimal input code,

12 for ICM7562, 10 for ICM7542 and 8 for ICM7522.

Output Buffer Amplifier

The Dual DAC has 2 output amplifiers connected in a gain

of 2 configuration. These amplifiers have a wide output

voltage swing. The actual swing of the output amplifiers will

be limited by offset error and gain error. See the

Applications Information section for a more detailed

discussion.

The output amplifier can drive a load of 2.0 K

GND in parallel with a 500 pF load capacitance.

The output amplifier has a full-scale typical settling time of

8

s and it dissipates about 100

A with a 3V supply

voltage.

Serial Interface and Input Logic

This dual DAC family uses a standard 3-wire connection

compatible with SPI/QSPI and Microwire interfaces. Data is

always loaded in 16-bit words which consist of 4 address

and control bits (MSBs) followed by 12 bits (see Figure .3).

The last 5 bits of this 12 bit word are also used for power

down control (see tables 1 and 2). Each DAC is double

buffered with an input latch and DAC latch.

Serial Data Input

SDI (Serial Data Input) pin is the data input pin for all DACs.

Data is clocked in on the falling edge of SCK which has a

Schmitt trigger internally to allow for noise immunity on the

SCK pin. This specially eases the use for opto-coupled

interfaces.

package is active low. This pin frames the input data for

synchronous loading and must be low when data is being

clocked into the part. There is an onboard counter on the

automatically transferred to a 16-bit input latch and the 4

bit control word (C3~C0) is then decoded and the

appropriate DAC is updated or loaded depending on the

control word (see Table 1). Chip Select pin must be pulled

high (level-triggered) and back low for the next data word

to be loaded in. This pin also disables the SCK pin

internally when pulled high.

The DAC has a double-buffered input with an input latch

and a DAC latch. The DAC output will swing to its new

value when data is loaded into the DAC latch. The user

has three options: loading only the input latch, updating the

DAC with data previously loaded into the input latch or

loading the input latch and updating the DAC at the same

time with a new code. The actual data that gets loaded into

the DAC latch is D11~D0 for the ICM7562, D9~D0 for the

ICM7542 and D7~D0 for the ICM 7522.

Power-Down Mode

The DAC have three Software-Selectable Power-Down

Output Impedances (1 K Ohm, 100 K Ohm and Hi-Z) as

additional safety feature for applications that drive

transducers or valves. The power down can be done with

loading the control word with 1111 (C0 to C3). Tthe

selection of the Output Impedance of DAC is controlled by

the last 5 bits. See Table 1 and Table 2 for details of

operation of this function.

Power-On Reset

There is a power-on reset on board that will clear the

contents of all the latches to all 0s on power-up and the

DAC voltage output will go to ground.

APPLICATIONS INFORMATION

Power Supply Bypassing and Layout Considerations

As in any precision circuit, careful consideration has to be

given to layout of the supply and ground. The return path

from the GND to the supply ground should be short with

low impedance. Using a ground plane would be ideal. The

supply should have some bypassing on it. A 10

F

tantalum capacitor in parallel with a 0.1 F ceramic with a

low ESR can be used. Ideally these would be placed as

close as possible to the device. Avoid crossing digital and

analog signals, specially the reference, or running them

close to each other.

Output Swing Limitations

However, offset and gain error limit this ability. Figure 4

illustrates how a negative offset error will affect the output.

The output will limit close to ground since this is single

supply part, resulting in a dead-band area. As a larger

input is loaded into the DAC the output will eventually rise

above ground. This is why the linearity is specified for a

starting code greater than zero.