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X25128PG Datasheet(PDF) 2 Page - IC MICROSYSTEMS |
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X25128PG Datasheet(HTML) 2 Page - IC MICROSYSTEMS |
2 / 15 page X25128 2 PIN DESCRIPTIONS Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input (SI) SI is the serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK) The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input. Chip Select (CS) When CS is high, the X25128 is deselected and the SO output pin is at high impedance and unless an internal write operation is underway, the X25128 will be in the standby power mode. CS low enables the X25128, placing it in the active power mode. It should be noted that after power-up, a high to low transition on CS is required prior to the start of any operation. Write Protect (WP) When WP is low and the nonvolatile bit WPEN is “1”, nonvolatile writes to the X25128 status register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvola- tile writes operate normally. WP going low while CS is still low will interrupt a write to the X25128 status register. If the internal write cycle has already been initiated, WP going low will have no effect on a write. The WP pin function is blocked when the WPEN bit in the status register is “0”. This allows the user to install the X25128 in a system with WP pin grounded and still be able to write to the status register. The WP pin func- tions will be enabled when the WPEN bit is set “0”. Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought low while SCK is Low. To resume commu- nication, HOLD is brought high, again while SCK is low. If the pause feature is not used, HOLD should be held high at all times. PIN CONFIGURATION PIN NAMES 3091 FM T01 Symbol Description CS Chip Select Input SO Serial Output SI Serial Input SCK Serial Clock Input WP Write Protect Input VSS Ground VCC Supply Voltage HOLD Hold Input NC No Connect 3091 FM 02 Not to scale 14 Lead SOIC NC 1 2 3 4 7 6 5 X24128 VSS NC NC NC NC .244” .344” 8 9 10 11 12 14 13 NC 8 Lead PDIP VCC HOLD SCK CS 1 2 3 4 6 7 8 X25128 VSS SI 5 .325” .430” SO WP CS SO WP VCC HOLD SCK SI 16 Lead SOIC NC 1 2 3 4 7 6 5 X25128 VSS NC NC NC NC NC .244” .394” 9 10 11 12 13 14 NC 8 16 15 NC CS SO WP VCC HOLD SCK SI |
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