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LF3312 Datasheet(PDF) 5 Page - LOGIC Devices Incorporated

Part # LF3312
Description  12-Mbit Frame Buffer / FIFO
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Manufacturer  LODEV [LOGIC Devices Incorporated]
Direct Link  http://www.logicdevices.com
Logo LODEV - LOGIC Devices Incorporated

LF3312 Datasheet(HTML) 5 Page - LOGIC Devices Incorporated

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DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
LOGIC Devices Incorporated
August 8, 2006 LDS.3312 O
Video Imaging Product
5
Operating Modes
Asynchronous single-channel FIFO mode (OPMODE = 3)
In OPMODE 3, the LF3312 is configured as a single channel First-In-First-Out 12Mbit memory, with
independent read and write clocks to allow for asynchronous operation. This mode is ideal for buffering or
burst data applications. Arbitrary write/read pointer jumping is supported in all FIFO modes. In this mode
the device can re-time a data stream according to a read sync signal (RSET or RCLR) and either ITU-R656
Timing Reference Signals (TRS) embedded within the incoming (video) data or the falling edge of a write
sync signal applied to ACLR, ASET, or AMARK.
As a single channel FIFO, the LF3312 must have AWCLK and BWCLK tied together as must be AWEN
with BWEN, and AIEN with BIEN. The input (write) and output (read) clocks need not be synchronous with
one another, although the memory core will eventually fill or empty if they differ in average frequency. After
it “fills,” the LF3312 continues writing and the oldest data gets written over. If the memory core “empties”
(and neither the read nor write pointer have been set or cleared during run-time) the read pointer stops
incrementing, and the device re-reads the last written sample until more data is written. In either case,
when the read and write addresses reach equality, the ACOLLIDE flag will go high, to alert the host. The
almost-full and almost-empty flags provide advance warning of these conditions whenever user-selected
“fullness” or “emptiness” thresholds, expressed in approximate eightieths of the memory core size, are
exceeded. For example, if the 1/80 and 79/80 thresholds are enabled, flag APE will go HIGH whenever the
read pointer lags behind the write pointer by less than 1/80 of the memory space, and flag APF will go HIGH
whenever the read pointer leads the write pointer by this amount. (Calculations are performed modulo the
total address space.) The data input and output are sequential and the timing between write and read sync
signals dynamically determines the effective delay (depth) of the FIFO.
The ‘stop reading when empty’ FIFO-mode behavior can be avoided by making sure LOAD is HIGH and
issuing any write or read pointer SET or CLR command at any time. This effectively gets the device out
of this ‘read-pointer-halting’ mode from that point onwards, but invalidates the flags. Random Access Mode
allows free manipulation of the r/w pointers, and never halts the read pointer without being commanded
to do so using AREN or BREN. Since Random Access mode naturally increments the r/w pointers
sequentially, like in FIFO mode, it may be a better mode to use if pointer manipulation of a single-channel
of memory is desired.
Dual-channel asynchronous FIFO mode (OPMODE = 7; power-on default)
OPMODE 7 operates identically to the single channel FIFO (OPMODE 3), with two independent chanels.
In dual-channel asynchronous FIFO mode, the device can accept two asynchronous data streams and
automatically adjust the latency of each to bring it into alignment with an output sync signal applied to RSET
or RCLR. Again, the user may reference input synchronization either to ACLR, ASET, BCLR, and BSET,
to AMARK and BMARK, or to embedded TRS. The data read/output clock need not be synchronous with
either of the two input clocks, which likewise need not be synchronous with one another. If memory core
A or B “empties“ or “fills“ completely, ACOLLIDE and/or BCOLLIDE respectively, will be set accordingly if
the write and read pointers collide.
The data Word that BMARK ‘marks’ (by going LOW during that xWCLK cycle) in the input data stream
will be the first synchronized AOUT/BOUT data word. If N full frames of Channel A data have been
loaded into AIN before the first Channel B data frame is loaded into BIN, the second frame of B channel
data will be synchronized to the (N+1)th Channel A frame. (there will be N frames difference between
Channel A and B).


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