TMS470R1VF338, TMS470R1VF348, TMS470R1VF3382, TMS470R1VF3482

16/32-BIT RISC FLASH MICROCONTROLLERS

SPNS077J – NOVEMBER 2001 – REVISED AUGUST 2006

10

POST OFFICE BOX 1443

Terminal Functions (Continued)

† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect

‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.

§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)

TERMINAL

INTERNAL

PULLUP/

DESCRIPTION

NAME

VF338

VF348

SERIAL PERIPHERAL INTERFACE 1 (SPI1)

SPI1CLK

5

5

3.3-V I/O

IPD

SPI1 clock. SPI1CLK can be programmed as a GIO pin.

SPI1ENA

1

1

SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.

SPI1SCS

2

2

SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.

SPI1SIMO

3

3

SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as

a GIO pin.

SPI1SOMI

4

4

SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as

a GIO pin.

SERIAL PERIPHERAL INTERFACE 2 (SPI2)

SPI2CLK

41

41

3.3-V I/O

IPD

SPI2 clock. SPI2CLK can be programmed as a GIO pin.

SPI2ENA

44

44

SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.

SPI2SCS

–45

SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin.

(This pin is not applicable to the VF338x device.)

SPI2SIMO

42

42

SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as

a GIO pin.

SPI2SOMI

43

43

SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as

a GIO pin.

ZERO-PIN PHASE-LOCKED LOOP (ZPLL)

OSCIN

8

8

1.8-V I

Crystal connection pin or external clock input

OSCOUT

7

7

1.8-V O

External crystal connection pin

PLLDIS

51

51

3.3-V I

IPD

Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator

becomes the system clock. If not in bypass mode, TI recommends that this

pin be connected to ground or pulled down to ground by an external resistor.

SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)

SCI1CLK

62

61

3.3-V I/O

IPD

SCI1 clock. SCI1CLK can be programmed as a GIO pin.

SCI1RX

64

63

3.3-V I/O

IPU

SCI1 data receive. SCI1RX can be programmed as a GIO pin.

SCI1TX

63

62

3.3-V I/O

IPU

SCI1 data transmit. SCI1TX can be programmed as a GIO pin.

SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)

SCI2RX

30

32

3.3-V I/O

IPU

SCI2 data receive. SCI2RX can be programmed as a GIO pin.

SCI2TX

31

33

3.3-V I/O

IPU

SCI2 data transmit. SCI2TX can be programmed as a GIO pin.

SYSTEM MODULE (SYS)

CLKOUT

59

58

3.3-V I/O

IPD

Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output

of SYSCLK, ICLK, or MCLK.

PORRST

21

21

3.3-V I

IPD

assert a power-on reset.

RST

10

10

3.3-V I/O

IPU

Bidirectional reset. The internal circuitry can assert a reset, and an external

system reset can assert a device reset. On this pin, the output buffer is

implemented as an open drain (drives low only).

To ensure an external reset is not arbitrarily generated, TI recommends

that an external pullup resistor be connected to this pin.