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AKD4420 Datasheet(PDF) 9 Page - Asahi Kasei Microsystems

Part # AKD4420
Description  192kHz 24-Bit Stereo ?誇 DAC with 2Vrms Output
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Manufacturer  AKM [Asahi Kasei Microsystems]
Direct Link  http://www.akm.com
Logo AKM - Asahi Kasei Microsystems

AKD4420 Datasheet(HTML) 9 Page - Asahi Kasei Microsystems

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[AK4420]
OPERATION OVERVIEW
System Clock
The external clocks required to operate the AK4420 are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically and then the internal master
clock is set to the appropriate frequency (Table 1).
The AK4420 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode,
and the analog output is forced to 0V(typ). When MCLK and LRCK are input again, the AK4420 is powered up. After
power-up, the AK4420 is in the power-down mode until MCLK and LRCK are input.
LRCK
MCLK (MHz)
fs
128fs
192fs
256fs
384fs
512fs
768fs
1152fs
Sampling
Speed
32.0kHz
-
-
-
-
16.3840
24.5760
36.8640
44.1kHz
-
-
-
-
22.5792
33.8688
-
48.0kHz
-
-
-
-
24.5760
36.8640
-
Normal
32.0kHz
8.192
12.288
44.1kHz
11.2896
16.9344
48.0kHz
12.288
18.432
88.2kHz
-
-
22.5792
33.8688
-
-
-
96.0kHz
-
-
24.5760
36.8640
-
-
-
Double
176.4kHz
22.5792
33.8688
-
-
-
-
-
Quad
192.0kHz
24.5760
36.8640
-
-
-
-
-
Table 1. system clock example
When MCLK= 256fs/384fs, the AK4420 supports sampling rate of 32kHz~96kHz (Table 2). But, when the sampling rate
is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK= 512fs/768fs.
MCLK
DR,S/N
256fs/384fs
102dB
512fs/768fs
105dB
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF pin can select between two serial
data modes as shown in Table 3. In all modes the serial data is MSB-first, two’s complement format and it is latched on
the rising edge of BICK. In one cycle of LRCK, eight “H” pulses or more must not be input to the DIF pin.
Mode
DIF
SDTI Format
BICK
Figure
0
L
24bit MSB justified
≥48fs
Figure 3
1
H
24bit I2S
Figure 4
≥48fs
Table 3. Audio Data Formats
MS0683-E-02
2007/12
- 9 -


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