HT48RA0-3/HT48CA0-3

Rev.1.10

6

October 12, 2007

Indirect Addressing Register

Location 00H is an indirect addressing register that is

not physically implemented. Any read/write operation to

[00H] accesses the data memory pointed to by MP

(01H). Reading location 00H itself indirectly will return

the result 00H. Writing indirectly results in no operation.

The memory pointer register MP (01H) is a 7-bit register.

Bit 7 of MP is undefined and reading will return the result

²1². Any writing operation to MP will only transfer the

lower 7-bits of data to MP.

Accumulator

The accumulator closely relates to ALU operations. It is

also mapped to location 05H of the data memory and is

capable of carrying out immediate data operations. Data

movement between two data memory locations has to

pass through the accumulator.

Arithmetic and Logic Unit

- ALU

This circuit performs 8-bit arithmetic and logic operation.

The ALU provides the following functions.

The ALU not only saves the results of a data operation but

also changes the contents of the status register.

Status Register

- STATUS

This 8-bit status register (0AH) contains the zero flag

(Z), carry flag (C), auxiliary carry flag (AC), overflow flag

(OV), power down flag (PDF) and watchdog time-out

flag (TO). It also records the status information and con-

trols the operation sequence.

S p e c i a l P u r p o s e

D a t a M e m o r y

I A R

M P

A C C

P C L

T B L P

T B L H

S T A T U S

P A

P B

T S R 0

T S R 1

C A R L 0

C A R L 1

C A R H 0

C A R H 1

G e n e r a l P u r p o s e

D a t a M e m o r y

( 3 2 B y t e s )

: U n u s e d

R e a d a s " 0 0 "

2 0 H

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

3 F H

RAM Mapping

Bit No.

Label

Function

0C

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-

tate through carry instruction.

1AC

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

2

Z

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

3OV

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

4

PDF

PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF

is set by executing the HALT instruction.

5TO

TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is

set by a WDT time-out.

6~7

¾

Unused bit, read as

²0²

Status (0AH) Register