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74LVTH125MTC Datasheet(PDF) 1 Page - Fairchild Semiconductor |
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74LVTH125MTC Datasheet(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page ©1998 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LVTH125 Rev. 1.4.0 January 2008 74LVTH125 Low Voltage Quad Buffer with 3-STATE Outputs Features ■ Input and output interface capability to systems at 5V VCC ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Live insertion/extraction permitted ■ Power Up/Down high impedance provides glitch-free bus loading ■ Outputs source/sink –32mA/+64mA ■ Functionally compatible with the 74 series 125 ■ Latch-up performance exceeds 500mA ■ ESD performance: – Human-body model > 2000V – Machine model > 200V – Charged-device model > 1000V General Description The LVTH125 contains four independent non-inverting buffers with 3-STATE outputs. These buffers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH125 is fabri- cated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintain- ing a low power dissipation. Ordering Information Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. Order Number Package Number Package Description 74LVTH125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVTH125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVTH125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide |
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