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D950-CORE Datasheet(PDF) 6 Page - STMicroelectronics |
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D950-CORE Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 89 page 6/89 D950-Core 2 PIN DESCRIPTION The following tables detail the D950-Core pin set. There is one table for each group of pins. The tables detail the pin name, type and a short description of the pin function. A diagram of the D950-Core I/O interface is contained at the end of the section. Table 2.1 DATA BUSES (70 PINS) Pin Name Type Description XD0-XD15 I/O X Data Bus. Hi-Z during cycles with no X-bus exchange. XA0-XA15 O X Address bus. Hi-Z when in Hold. XRD O X-bus read strobe. Active low. Hi-Z when in Hold. XWR O X-bus write strobe. Active low. Hi-Z when in Hold. XBS O X-bus strobe. Active low. Hi-Z when in Hold. Asserted low at the beginning of a valid X-bus cycle. YD0-YD15 I/O Y Data Bus. Hi-Z during cycles with no Y-bus exchange. YA0-YA15 O Y Address bus. Hi-Z when in Hold. YRD O Y-bus read strobe. Active low. Hi-Z when in Hold. YWR O Y-bus write strobe. Active low. Hi-Z when in Hold. YBS O Y-bus strobe. Active low. Hi-Z when in Hold. Asserted low at the beginning of a valid Y-bus cycle. 3 |
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