PCA9625 datasheet(7/33 Pages) NXP

Part #	PCA9625

Description	16-bit Fm I2C-bus 100 mA 24 V LED driver

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Manufacturer	NXP [NXP Semiconductors]

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7 / 33 page

PCA9625_2

Product data sheet

Rev. 02 — 15 January 2008

7 of 33

NXP Semiconductors

PCA9625

16-bit Fm+ I2C-bus 100 mA 24 V LED driver

The last bit of the address byte deﬁnes the operation to be performed. When set to logic 1

a read is selected, while a logic 0 selects a write operation.

7.1.2 LED All Call I2C-bus address

• Default power-up value (ALLCALLADR register): E0h or 1110 000

• Programmable through I2C-bus (volatile programming)

• At power-up, LED All Call I2C-bus address is enabled. PCA9625 sends an ACK when

E0h (R/W = 0) or E1h (R/W = 1) is sent by the master.

See Section 7.3.8 “ALLCALLADR, LED All Call I2C-bus address” for more detail.

Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used

as a regular I2C-bus slave address since this address is enabled at power-up. All the

PCA9625s on the I2C-bus will acknowledge the address if sent by the I2C-bus master.

7.1.3 LED Sub Call I2C-bus addresses

• 3 different I2C-bus addresses can be used

• Default power-up values:

– SUBADR1 register: E2h or 1110 001

– SUBADR2 register: E4h or 1110 010

– SUBADR3 register: E8h or 1110 100

• Programmable through I2C-bus (volatile programming)

• At power-up, Sub Call I2C-bus addresses are disabled. PCA9625 does not send an

ACK when E2h (R/W = 0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W = 1), or

E8h (R/W = 0) or E9h (R/W = 1) is sent by the master.

See Section 7.3.7 “SUBADR1 to SUBADR3, I2C-bus subaddress 1 to 3” for more detail.

Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus

slave addresses as long as they are disabled.

7.1.4 Software Reset I2C-bus address

The address shown in Figure 4 is used when a reset of the PCA9625 needs to be

performed by the master. The Software Reset address (SWRST Call) must be used with

R/W = logic 0. If R/W = logic 1, the PCA9625 does not acknowledge the SWRST. See

Section 7.6 “Software Reset” for more detail.

Fig 3.

Slave address

R/W

002aab319

A6

A5

A4

A3

A2

A1

A0

hardware selectable

slave address

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