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P5CC040XS Datasheet(PDF) 7 Page - NXP Semiconductors |
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P5CC040XS Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 18 page P5CX012_02X_40_73_80_144_FAM_SDS_3 © NXP B.V. 2008. All rights reserved. Objective short data sheet Rev. 03 — 24 January 2008 7 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 2.3 Security features I Enhanced security sensors: N Low and high clock frequency sensor N Low and high temperature sensor N Low and high supply voltage sensor N Single Fault Injection (SFI) attack detection N Light sensors (included integrated memory light sensor functionality) I Electronic fuses for safeguarded mode control I Active shielding I Unique ID for each die I Clock input filter for protection against spikes I Power-up and power-down reset I Optional programmable card disable feature I Memory security (encryption and physical measures) for RAM, EEPROM and ROM I Memory Management Unit (MMU) including memory protection: N Secure multi application operating systems via two different operation modes: System mode and User mode N OS controlled access restriction mechanism to peripherals in User mode N Memory mapping up to 8-MB code memory N Memory mapping up to 8-MB (64-kbit) data memory I Optional disabling of ROM read instructions by code executed in EEPROM I Optional disabling of any code execution out of RAM I EEPROM programming: N No external clock N Hardware sequencer controlled N On-chip high voltage generation N Enhanced error correction mechanism I 64-B or 128-B EEPROM for customer-defined Security FabKey. Featuring batch, wafer or die-individual security data, included encrypted diversification features on request I 14 B user write protected security area in EEPROM (byte access, inhibit functionality per byte) I 32 B write once security area in EEPROM (bit access) I 32 B user read only area in EEPROM (byte access) I Customer specific EEPROM initialization available |
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