ICS83904AG-02 datasheet(1/15 Pages) IDT

Part #	ICS83904AG-02

Description	LOW SKEW, 1-TO-4, CRYSTAL-TOLVCMOS/LVTTL FANOUT BUFFER

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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LOW SKEW, 1-TO-4, CRYSTAL-TO-

LVCMOS/LVTTL FANOUT BUFFER

ICS83904-02

IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER

1

ICS83904AG-02 REV. A SEPTEMBER 12, 2007

FEATURES

• Four LVCMOS/LVTTL outputs,

19

Ω typical output impedance @ V

DD = VDDO = 3.3V

• Two Crystal oscillator input pairs

One LVCMOS/LVTTL clock input

• Crystal input frequencry range: 12MHz – 38.88MHz

• Output frequency: 200MHz (maximum)

• Output Skew: 40ps (maximum) @ V

DD = VDDO = 3.3V

• RMS phase jitter @ 25MHz output, using a 25MHz crystal

(100Hz – 1MHz): 0.16ps (typical) @ V

DD = VDDO = 3.3V

• RMS phase noise at 25MHz:

Offset

Noise Power

100Hz ............. -118.4 dBc/Hz

1kHz ............. -141.5 dBc/Hz

10kHz ............. -157.2 dBc/Hz

100kHz ............. -157.2 dBc/Hz

• Supply Voltage Modes:

(Core/Output)

3.3V/3.3V

3.3V/2.5V

3.3V/1.8V

2.5V/2.5V

2.5V/1.8V

• 0°C to 70°C ambient operating temperature

• Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

GENERAL DESCRIPTION

The ICS83904-02 is a low skew, high perfor-

mance 1-to-4 Crystal Oscillator/Crystal-to-LVCMOS

Fanout Buffer and a member of the HiPerClockS™

family of High Performance Clock Solutions from IDT.

The ICS83904-02 has selectable single-ended clock

or two crystal-oscillator inputs. There is an output enable to

disable the outputs by placing them into a high-impedance state.

Guaranteed output and par t-to-par t skew characteristics

make the ICS83904-02 ideal for those applications demand-

ing well defined performance and repeatability.

HiPerClockS™

ICS

BLOCK DIAGRAM

OE

CLK_SEL0

CLK_SEL1

CLK

Q0

Q1

Q2

Q3

OSC

0 0

0 1

1 0

1 1

Pullup

ICS83904-02

16-Lead TSSOP

4.4mm x 5.0mm x 0.92mm

package body

G Package

Top View

Pulldown

XTAL_IN0

XTAL_OUT0

XTAL_IN1

XTAL_OUT1

Pulldown

CLK_SEL0

XTAL_OUT0

XTAL_IN0

VDD

XTAL_IN1

XTAL_OUT1

CLK_SEL1

CLK

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDDO

Q0

Q1

GND

Q2

Q3

VDDO

OE

PIN ASSIGNMENT

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